Trench buried bit line memory devices and methods thereof
View Patent ↗A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.
1. A method of forming a memory cell, the method comprising:
forming a trench in a base substrate generally parallel and along side a continuous strip of active area;
lining said trench with a spacer;
depositing a conductive bit line within said trench;
etching said conductive bit line back so that an uppermost surface of said conductive bit line is at a distance within said base substrate defined by a combined distance of a junction depth plus a depletion width of a transistor; and
coupling a bit line strap between said conductive bit line and said active area at least about said uppermost surface of said base substrate.
2. The method of claim 1 , wherein said base substrate has a first base layer and a second base layer.
3. The method of claim 2 , wherein said continuous strip of active area is formed on said first base layer of said base substrate.
4. The method of claim 2 , wherein further comprising;
etching said conductive bit line back below an uppermost surface of said second base layer of said base substrate.
5. The method of claim 1 , wherein said spacer is formed by thermally growing a first layer of oxide and depositing a second layer of oxide over said first layer of oxide.
6. The method of claim 5 , wherein said spacer further comprises depositing a nitride layer over said second layer of oxide.
7. The method of claim 1 , wherein said spacer is formed to have a thickness of about one fourth the minimum realizable feature size, wherein the minimum realizable feature size is about 1000 Angstroms.
8. The method of claim 1 , wherein etching back is recessed within said base substrate such that an uppermost surface of said conductive bit line is at a distance that is sufficiently deep to avoid gate induced drain leakage effects.
9. The method of claim 1 , further comprising:
creating an insulating capping layer within said trench over said conductive bit line.
10. The method of claim 9 , wherein said insulating cap comprises a layer of nitride and a layer of insulating material over said nitride layer.
11. The method of claim 9 , wherein creating said insulating cap further comprises:
forming a capping layer of nitride over said conductive bit line; and
forming a capping insulating material of HDP over said capping layer of nitride.
12. The method of claim 1 , further comprising:
forming a transistor, including a first source/drain region and a second source/drain region, in said active area; and
coupling a word line to said transistor defining a transistor gate.
13. The method of claim 12 , further comprising:
forming a capacitor over said base substrate; and
coupling said capacitor to said transistor electrically.
14. The method of claim 1 , wherein said bit line strap is isolated from said active area by an insulative spacer.
15. The method of claim 1 , wherein said conductive bit line comprises a layer of titanium alloy containing tungsten.
16. A method of forming a memory cell, the method comprising:
forming a trench in a base substrate generally parallel and along side a continuous strip of active area, wherein said base substrate has a first base layer and a second base layer;
lining said trench with a spacer;
depositing a conductive bit line within said trench;
etching said conductive bit line back below an uppermost surface of said second base layer of said base substrate so that an uppermost surface of said conductive bit line is at a distance defined by a combined distance of a junction depth plus a depletion width of a transistor; and
coupling a bit line strap between said conductive bit line and said active area at least about said uppermost surface of said base substrate.
17. A method of forming a memory cell, the method comprising:
forming a trench in a base substrate generally parallel and along side a continuous strip of active area;
lining a portion of the walls of said trench with a spacer;
depositing a conductive bit line within said trench;
etching said conductive bit line below an uppermost surface of said base substrate so that an uppermost surface of said conductive bit line is at a distance defined by a combined distance of a junction depth plus a depletion width of a transistor;
forming a transistor, including a first source/drain region and a second source/drain region, in said active area;
coupling a bit line strap between said conductive bit line and said active area at least about said uppermost surface of said base substrate; and
coupling said bit line strap to said first source/drain region through said portion of said walls of said trench.
18. The method of claim 17 , wherein etching back is recessed within said base substrate such that an uppermost surface of said conductive bit line is at a distance that is sufficiently deep to avoid gate induced drain leakage effects.
19. A method of forming a memory cell, the method comprising:
forming a trench in a base substrate generally parallel and along side a continuous strip of active area;
forming a transistor in a first type well in said base substrate comprising a channel between a first source/drain region and a second source/drain region;
lining a portion of the walls of said trench with a spacer;
depositing a conductive bit line within said trench;
etching said conductive bit line below an uppermost surface of said base substrate so that an uppermost surface of said conductive bit line is at a distance within said base substrate defined by a combined distance of a junction depth plus a depletion width of a transistor;
coupling said bit line strap to said conductive bit line and said first source/drain region of said transistor.
20. A method of forming a memory cell, the method comprising:
forming a trench in a base substrate generally parallel and along side a continuous strip of active area that is etched to a depth greater than twice a minimum realizable feature size, wherein the minimum realizable feature size is about 1000 Angstroms;
lining said trench with a spacer;
depositing a conductive bit line within said trench;
etching said conductive bit line below an uppermost surface of said base substrate so that an uppermost surface of said conductive bit line is at a distance within said base substrate defined by a combined distance of a junction depth plus a depletion width of a transistor; and
coupling a bit line strap between said conductive bit line and said active area at least about said uppermost surface of said base substrate.
21. The method of claim 20 , wherein said base substrate has a first base layer and a second base layer.
22. The method of claim 21 , wherein said first base layer is doped with a first type of impurity and said second base layer comprises a buried layer doped with a second type impurity.
23. The method of claim 21 , wherein said first base layer comprises a P-type semiconductor material and said second base layer comprises an N+ buried layer.
24. The method of claim 21 , wherein said first base layer comprises a semiconductor layer and said second base layer comprises an insulator layer.
25. A method of forming a memory cell, the method comprising:
forming a P-type well within a base substrate;
forming an N-type active area within said P-type well;
forming a trench in said base substrate generally adjacent to said N-type active area;
lining at least a portion of the walls of said trench with a spacer;
depositing a conductive bit line within said trench;
etching said conductive bit line below an uppermost surface of said base substrate so that an uppermost surface of said conductive bit line is at a distance within said base substrate defined by a combined distance of a junction depth plus a depletion width of a transistor; and
coupling a bit line strap between said conductive bit line and said N-type active area at least about said uppermost surface of said base substrate and through said at least said portion of said walls of said trench.