Semiconductor device and method of manufacturing the same
View Patent ↗According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.
1. A semiconductor device, comprising:
a semiconductor substrate of a first conductive type;
a first well of a second conductive type formed in the semiconductor substrate, where the second conductive type being opposite type of the first conductive type;
a second well of the first conductive type formed beside the first well in the semiconductor substrate; and
a third well of the second conductive type which is formed beside the second well in the semiconductor substrate, and which is deeper than the second well,
wherein a fourth well of the first conductive type deeper than the second well is formed between the second and third wells in the semiconductor substrate, the fourth well being in contact with the second well.
2. The semiconductor device according to claim 1 , wherein the fourth well is also formed between the first and second wells in the semiconductor substrate.
3. The semiconductor device according to claim 2 , wherein the first well is deeper than the second well.
4. The semiconductor device according to claim 1 , wherein the fourth well is formed to surround the third well.
5. The semiconductor device according to claim 1 , wherein:
a fifth well of the first conductive type is formed beside the first well in the semiconductor substrate; and
a MOS transistor with a CMOS structure is formed in each of the first and fifth wells.
6. The semiconductor device according to claim 1 , wherein:
an isolation well of the first conductive type and a sixth well of the second conductive type are formed side-by-side beside the third well in the semiconductor substrate; and
the third and sixth wells are isolated from each other by the isolation well.
7. The semiconductor device according to claim 1 , wherein first to third MOS transistors are formed respectively in the first to third wells.
8. The semiconductor device according to claim 1 , wherein a flash memory cell is formed in the semiconductor substrate.
9. A semiconductor device, comprising:
a semiconductor substrate of a first conductive type;
a first well of a second conductive type formed in the semiconductor substrate, where the second conductive type being opposite type of the first conductive type;
a second well of the first conductive type formed beside the first well in the semiconductor substrate; and
a third well of the second conductive type which is formed beside the second well in the semiconductor substrate, and which is deeper than the second well, wherein:
a fourth well of the first conductive type deeper than the second well is formed between the second and third wells in the semiconductor substrate; the fourth well being in contact with the second well, and
an absolute value of a voltage applied to the third well is larger than any one of an absolute value of voltages applied to the first well and an absolute value of voltages applied to the second well.
10. The semiconductor device according to claim 9 , wherein the fourth well is also formed between the first and second wells in the semiconductor substrate.
11. The semiconductor device according to claim 9 , wherein the first well is deeper than the second well.
12. The semiconductor device according to claim 9 , wherein the fourth well is formed to surrounds the third well.
13. The semiconductor device according to claim 9 , wherein:
first to third MOS transistors are formed respectively in the first to third wells; and
an operating voltage of the third MOS transistor is higher than any one of an operating voltage of the first MOS transistor and an operating voltage of the second MOS transistor.
14. The semiconductor device according to claim 9 , wherein a flash memory cell is formed in the semiconductor substrate.
15. A method of manufacturing a semiconductor device, comprising:
forming a first well of a second conductive type in a semiconductor substrate of a first conductive type, where the second conductive type being opposite type of the first conductive type;
forming a second well of the first conductive type beside the first well in the semiconductor substrate;
forming a third well of the second conductive type deeper than the second well beside the second well in the semiconductor substrate; and
forming a fourth well of the first conductive type deeper than the second well between the second and third wells in the semiconductor substrate, the fourth well being in contact with the second well.
16. The method of manufacturing a semiconductor device according to claim 15 , wherein, when forming the fourth well, the fourth well is formed in a planar shape which is obtained by enlarging an outline of the third well to surround the third well.
17. The method of manufacturing a semiconductor device according to the claim 15 , further comprising:
forming a fifth well of the first conductive type beside the first well in the semiconductor substrate in the step of forming the fourth well; and
forming a MOS transistor with a CMOS structure in each of the first and fifth wells.
18. The method of manufacturing a semiconductor device according to claim 15 , further comprising:
forming a sixth well of the second conductive type in the semiconductor substrate,
wherein, when forming the fourth well, an isolation well of the first conductive type is formed between the third and sixth wells in the semiconductor substrate, and the third and sixth wells are isolated from each other by the isolation well.
19. The method of manufacturing a semiconductor device according to claim 15 , further comprising:
forming first to third MOS transistors respectively in the first to third wells.
20. The method of manufacturing a semiconductor device according to claim 15 , further comprising:
forming a flash memory cell in the semiconductor substrate.
21. A semiconductor device, comprising:
a semiconductor substrate of a first conductive type;
a first well of a second conductive type formed in the semiconductor substrate, where the second conductive type being opposite type of the first conductive type;
a second well of the first conductive type formed in the semiconductor substrate, the second well being formed beside the first well and neighboring the first well; and
a third well of the second conductive type which is formed in the semiconductor substrate and neighboring the second well, and which is deeper than the second well,
wherein a fourth well of the first conductive type deeper than the second well is formed between the second and third wells in the semiconductor substrate, the fourth well neighboring the second well.
22. A semiconductor device, comprising:
a semiconductor substrate of a first conductive type;
a first well of a second conductive type formed in the semiconductor substrate, where the second conductive type being opposite type of the first conductive type;
a second well of the first conductive type formed in the semiconductor substrate, the second well being formed beside the first well and neighboring the first well; and
a third well of the second conductive type which is formed in the semiconductor substrate and neighboring the second well, and which is deeper than the second well, wherein:
a fourth well of the first conductive type deeper than the second well is formed between the second and third wells in the semiconductor substrate; the fourth well neighboring the second well, and
an absolute value of a voltage applied to the third well is larger than any one of an absolute value of voltages applied to the first well and an absolute value of voltages applied to the second well.
23. A method of manufacturing a semiconductor device, comprising:
forming a first well of a second conductive type in a semiconductor substrate of a first conductive type, where the second conductive type being opposite type of the first conductive type;
forming a second well of the first conductive type in the semiconductor substrate, the second well being formed beside the first well and neighboring the first well;
forming a third well of the second conductive type deeper than the second well in the semiconductor substrate, the third well neighboring the second well; and
forming a fourth well of the first conductive type deeper than the second well between the second and third wells in the semiconductor substrate, the fourth well neighboring the second well.