IP Library Granted Patent US 7,256,116
Granted Patent B2
US 7,256,116 · App. 11/589,464 · Granted Aug 14, 2007

Method for fabricating semiconductor components having encapsulated, bonded, interconnect contacts on redistribution contacts

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,256,116
App. No.
11/589,464
Granted
Aug 14, 2007
Kind
B2
Abstract

A method for fabricating a semiconductor component includes the steps of providing a semiconductor die, forming a plurality of redistribution contacts on the die, forming a plurality of interconnect contacts on the redistribution contacts, and forming an insulating layer on the interconnect contacts while leaving the tip portions exposed. The method also includes the step of forming terminal contacts on the interconnect contacts, or alternately forming conductors in electrical communication with the interconnect contacts and then forming terminal contacts in electrical communication with the conductors.

Claims (40)

1. A method for fabricating a semiconductor component comprising:

providing a plurality of redistribution contacts on a semiconductor die;

forming a plurality of interconnect contacts on the redistribution contacts having tip portions;

forming an insulating layer on the die and on the interconnect contacts with the tip portions exposed; and

forming a plurality of terminal contacts on the insulating layer in electrical contact with the tip portions, by forming metallization layers on the tip portions and metal bumps or balls on the metallization layers.

2. The method of claim 1 wherein the redistribution contacts have a pattern which is different than bond pads for the die.

3. The method of claim 1 wherein the forming the terminal contacts step comprises stenciling, solder reflow, electrolytic deposition, electroless deposition or bonding of pre-fabricated balls.

4. The method of claim 1 wherein the forming the insulating layer step comprises depositing and then etching a polymer material to expose the tip portions.

5. The method of claim 1 wherein the forming the insulating layer step comprises depositing the insulating layer to a thickness less than a height of the interconnect contacts.

6. The method of claim 1 wherein the forming the interconnect contacts step comprises bonding wires, studs or ribbons to the redistribution contacts.

7. The method of claim 1 wherein the forming the interconnect contacts step comprises depositing metal bumps on the redistribution contacts.

8. The method of claim 1 wherein the forming the interconnect contacts step comprises bonding balls to the redistribution contacts.

9. The method of claim 1 wherein the semiconductor die is contained on a substrate comprising a plurality of semiconductor dice, each forming step is performed on all of the semiconductor dice, and following the forming the insulating layer step, singulating the semiconductor dice from the substrate.

10. The method of claim 9 wherein the substrate comprises a semiconductor wafer.

11. A method for fabricating a semiconductor component comprising:

providing a semiconductor die comprising a plurality of redistribution contacts;

forming a plurality of interconnect contacts on the redistribution contacts having tip portions;

forming an insulating layer on the die configured to substantially encapsulate the interconnect contacts with the tip portions exposed;

forming a plurality of conductors on the insulating layer in electrical communication with the tip portions; and

forming a plurality of terminal contacts on the insulating layer in electrical communication with the conductors.

12. The method of claim 11 wherein the forming the insulating layer step comprises depositing and etching a polymer material.

13. The method of claim 11 wherein the forming the interconnect contacts step comprises wire bonding wires to the redistribution contacts and then severing the wires.

14. The method of claim 11 wherein the forming the terminal contacts step comprises forming metal bumps or balls on the insulating layer.

15. The method of claim 11 wherein the forming the interconnect contacts step comprises bonding studs or ribbons to the redistribution contacts.

16. The method of claim 11 wherein the forming the interconnect contacts step comprises depositing metal bumps on the redistribution contacts.

17. The method of claim 11 wherein the forming the interconnect contacts step comprises bonding balls to the redistribution contacts.

18. A method for fabricating a semiconductor component comprising:

providing a substrate comprising a plurality of semiconductor dice having a plurality of redistribution contacts in a first pattern;

forming a plurality of interconnect contacts on the redistribution contacts having tip portions;

forming an insulating layer on the dice and on the interconnect contacts with the tip portions exposed;

forming a plurality of conductors on the insulating layer in physical contact with the tip portions;

forming a plurality of terminal contacts on the insulating layer in a second pattern in electrical communication with the conductors; and

singulating the dice from the substrate.

19. The method of claim 18 wherein the forming the insulating layer step comprises depositing and etching a polymer layer to a thickness less than a height of the interconnect contacts.

20. The method of claim 18 wherein the forming the insulating layer step comprises depositing a polymer material to a thickness less than a height of the interconnect contacts.

21. The method of claim 18 wherein the terminal contacts comprise balls and the second pattern comprises a grid array.

22. The method of claim 18 wherein the forming the interconnect contacts step comprises wire bonding wires to the redistribution contacts and then severing the wires.

23. The method of claim 18 wherein the substrate comprises a semiconductor wafer.

24. The method of claim 18 wherein the interconnect contacts comprise an element selected from the class consisting of posts, studs, bumps, balls and ribbons.

25. The method of claim 18 wherein the redistribution contacts comprise a metal selected from the group consisting of Ni, Cu, Au, Ag, Pt, Pd, Sn, Zn and alloys of these metals.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →