Semiconductor memory device
View Patent ↗In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting a plurality of bit line pairs and connecting the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides.
1. A semiconductor memory device comprising:
a shared sense amplifier portion;
a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion;
a pair of transfer gates disposed on the opposite sides of the shared sense amplifier portion and between the pair of memory cell portions and the shared sense amplifier portion; and
bit lines which constitute a plurality of bit line pairs and which connect the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion,
wherein the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides, and
wherein the shared sense amplifier portion comprises a first shared sense amplifier with the bit lines in the bit line pair of the plurality of bit line pairs twisted and a second shared sense amplifier with the bit lines in a different bit line pair of the plurality of bit line pairs untwisted, the first and the second shared sense amplifiers being alternately arranged.
2. The semiconductor memory device according to claim 1 , wherein each of the pair of transfer gates carries out clocking to temporarily disconnect each of the pair of memory cell portions and the shared sense amplifier portion and to thereby amplify an inside part of the shared sense amplifier portion.
3. The semiconductor memory device according to claim 1 , wherein the bit lines in the bit line pair are twisted by a ring-shaped gate electrode of a transistor in the shared sense amplifier portion.
4. The semiconductor memory device according to claim 3 , wherein a part of the gate electrode is used as a wiring.
5. The semiconductor memory device according to claim 1 , wherein the bit lines in the bit line pair are twisted by a wiring layer formed in a well isolating region of the shared sense amplifier portion.
6. A shared sense amplifier portion for use in a semiconductor memory device comprising: a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion; a pair of transfer gates disposed on the opposite sides of the shared sense amplifier portion and between the pair of memory cell portions and the shared sense amplifier portion; and bit lines which constitute a plurality of bit line pairs and which connect the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion; wherein
the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a position corresponding to a substantial center between the pair of transfer gates on the opposite sides, and
wherein the shared sense amplifier portion comprises a first shared sense amplifier with the bit lines in the bit line pair of the plurality of bit line pairs twisted and a second shared sense amplifier with the bit lines in a different bit line pair of the plurality of bit line pairs untwisted, the first and the second shared sense amplifiers being alternately arranged.
7. The shared sense amplifier portion according to claim 6 , wherein the bit lines in the bit line pair are twisted by a ring-shaped gate electrode of a transistor.
8. The shared sense amplifier portion according to claim 7 , wherein a part of the gate electrode is used as a wiring.
9. The shared sense amplifier portion according to claim 6 , wherein the bit lines in the bit line pair are twisted by a wiring layer formed in a well isolating region.