System monitor in a programmable logic device
Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or reconfiguring the system monitor during operation thereof. The system monitor includes an analog-to-digital converter which is reconfigurable responsive to input via a dynamic reconfiguration port.
1. A system monitor circuit in an integrated circuit comprising:
an analog-to digital converter (ADC) configured to monitor a plurality of sensors;
a calibration circuit for calibrating an output of the ADC using a set value in a first register;
a filter circuit for filtering an output of the calibration circuit or an output of the ADC; and
a alarm circuit configured to determine an alarm condition by comparing the output of the calibration circuit or an output of the ADC or an output of the filter circuit with a set value in a second register.
2. The system monitor circuit of claim 1 further comprising: a microcontroller coupled to the ADC.
3. The system monitor circuit of claim 2 wherein the microcontroller is coupled to a read-only memory.
4. The system monitor circuit of claim 2 wherein the microcontroller is coupled to a random access memory.
5. The system monitor circuit of claim 1 further comprising: a hardwired PicoBlaze microcontroller coupled to a memory, the memory including the first and second registers.
6. The system monitor circuit of claim 1 further comprising: a memory coupled to a channel sequencer, the channel sequencer selecting a channel of the ADC for automatic monitoring.
7. A system monitor circuit in an integrated circuit comprising:
selection circuitry coupled to a plurality of sensors,
the selection circuitry configurable to select one of the plurality of sensors responsive to a first portion of control information;
an analog-to digital converter (ADC) configured to monitor the selected sensor
the ADC configurable responsive to a second portion of the control information;
a calibration circuit for calibrating an output of the ADC using a set value in a first register;
a filter circuit for filtering an output of the calibration circuit or an output of the ADC; and
a alarm circuit configured to determine an alarm condition by comparing the output of the calibration circuit or an output of the ADC or an output of the filter circuit with a set value in a second register.
8. The system monitor circuit of claim 7 further comprising: a microcontroller coupled to the ADC.
9. The system monitor circuit of claim 8 wherein the microcontroller is coupled to a read-only memory.
10. The system monitor circuit of claim 8 wherein the microcontroller is coupled to a random access memory.
11. The system monitor circuit of claim 7 further comprising: a hardwired PicoBlaze microcontroller coupled to a memory, the memory including the first and second registers.
12. The system monitor circuit of claim 7 further comprising: a memory coupled to a channel sequencer, the channel sequencer selecting a channel of the ADC for automatic monitoring.