Semiconductor device, method of forming wiring pattern, and method of generating mask wiring data
A semiconductor device includes a first wiring portion and a second wiring portion. The first wiring portion is configured to include a plurality of fine wirings placed densely. The second wiring portion configured to include a wiring, which is connected to one of the plurality of fine wirings in the same wiring layer, and of which outside dimension is larger than that of the one of the plurality of fine wirings. The wiring of the second wiring portion is composed of a peripheral wiring which circles an outer periphery of the wiring.
1 . A semiconductor device comprising:
a first wiring portion configured to include a plurality of fine wirings placed densely; and
a second wiring portion configured to include a wiring, which is connected to one of said plurality of fine wirings in the same wiring layer, and of which outside dimension is larger than that of said one of said plurality of fine wirings,
wherein said wiring of said second wiring portion is composed of a peripheral wiring which circles an outer periphery of said wiring.
2 . The semiconductor device according to claim 1 , wherein a data rate of said second wiring portion is limited to 50% or less, when a value equal to two times of said data rate of said first portion is used as a basic data rate.
3 . The semiconductor device according to claim 1 , wherein a wiring width of each of said plurality of fine wirings is equal to 0.1 μm or less.
4 . The semiconductor device according to claim 1 , wherein said second wiring portion further includes;
a via which is formed long and continuously along on said peripheral wiring.
5 . The semiconductor device according to claim 1 , wherein said second wiring portion further includes:
a second peripheral wiring which is connected to said peripheral wiring in the same wiring layer, circles an outer periphery of an area of a pad, and is connected to said pad through vias on said second peripheral wiring.
6 . The semiconductor device according to claim 1 , wherein said wiring of said second wiring portion is a lead-out wiring, and said first wiring portion is included in a macro.
7 . The semiconductor device according to claim 1 , wherein said wiring of said second wiring portion is a lead-out wiring, and said first wiring portion is included in a TEG (Test Element Group).
8 . A method of forming wiring pattern comprising:
(a) providing an existing pattern for wirings, wherein said wirings includes:
a first wiring portion configured to include a plurality of fine wirings placed densely, and
a second wiring portion configured to include a wiring, which is connected to one of said plurality of fine wirings in the same wiring layer, and of which outside dimension is larger than that of said one of said plurality of fine wirings; and
(b) forming a peripheral wiring which circles an outer periphery of said wiring of said second wiring portion by remaining said outer periphery of said wiring while removing an inside of said outer periphery of said wiring.
9 . The method of forming wiring pattern according to claim 8 , wherein said step (b) includes:
(b 1 ) forming a via which is long and continuously along on said peripheral wiring.
10 . The method of forming wiring pattern according to claim 8 , wherein said step (b) includes:
(b 2 ) forming a second peripheral wiring which is connected to said peripheral wiring in the same wiring layer, and circles an outer periphery of an area of a pad.
11 . A method of generating mask wiring data comprising:
(a) providing an existing mask wiring data for wirings, wherein said wirings includes:
a first wiring portion configured to include a plurality of fine wirings placed densely, and
a second wiring portion configured to include a wiring, which is connected to one of said plurality of fine wirings in the same wiring layer, and of which outside dimension is larger than that of said one of said plurality of fine wirings; and
(b) forming a mask wiring data having a data for a peripheral wiring by remaining data for an outer periphery of said wiring while removing data for an inside of said outer periphery of said wiring.
12 . The method of generating mask wiring data according to claim 11 , wherein said step (b) includes;
(b 1 ) forming said mask wiring data having a data for a via formed long and continuously along on said peripheral wiring.
13 . The method of generating mask wiring data according to claim 11 , wherein said step (b) includes:
(b 2 ) forming said mask wiring data having a data for a second peripheral wiring which is connected to said peripheral wiring in the same wiring layer, and circles an outer periphery of an area of a pad.