Processing of multiple cells in a network device with two reads and two writes on one clock cycle

1. A network device for processing packet data, the network device comprising:

a first plurality of data communication ports;

a second plurality of data communication ports; and

a packet data processing pipeline coupled with the first and second pluralities of data communication ports, the packet data processing pipeline comprising:

a first ingress module coupled with the first plurality of data communication ports;

a second ingress module coupled with the second plurality of data communication ports, wherein the first ingress module and the second ingress module are independent of one another, arranged in a parallel fashion and each configured to perform switching functions on respective incoming packet data;

a memory management unit (MMU) coupled with the two more ingress modules, the MMU being configured to store the incoming packet data in a memory; and

two or more egress modules coupled with the MMU, the two or more egress modules being configured to transmit the incoming packet data, respectively, to two or more corresponding egress ports, the two or more egress modules being arranged in a parallel fashion,

wherein the MMU is further configured to receive packet data using a network device clock signal operating at a clock speed for the network device and write the data to the memory using a multiplied clock signal operating at a multiplied clock speed that is greater than the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the two or more egress modules at the clock speed for the network device, where the multiplied clock signal is used to sample the network device clock signal to place timing domains of the multiplied clock signal and the network device clock signal in phase.

2. The network device according to claim 1 , wherein the multiplied clock speed comprises a doubled clock speed that is double the clock speed for the network device clock signal.

3. The network device according to claim 1 , wherein the MMU is further configured to write to and read from the memory four input/output values pipelined together every clock cycle of the clock signal for the network device.

4. The network device according to claim 3 , wherein each of the input/output values contains address, command and data components.

5. The network device according to claim 3 , wherein the MMU comprises a series of flip-flops and at least one flip-flop is configured to receive each of the four input/output values, where the series of flip-flops is configured to operate at the multiplied clock speed.

6. The network device according to claim 3 , wherein the MMU is further configured to create a setup and hold margin with the data in the multiplied clock signal timing domain to facilitate the capture of the data into the network device clock signal timing domain.

7. The network device according to claim 1 , wherein the MMU is further configured to tolerate a jitter of one eighth of a clock cycle of the clock for the network device clock signal timing domain and still operate correctly.

8. A method for processing packet data in a packet processing pipeline of a network device, the method comprising:

receiving, at two or more parallel ingress ports of the packet processing pipeline, packet data to be stored, in a memory, by a memory management unit (MMU) of the packet processing pipeline, the packet data being received using a network device clock signal operating at a clock speed for the network device, wherein the packet data is received at a first ingress port of the two or more parallel ingress ports from a first plurality of data communication ports of the network device and at a second ingress port of the two or more parallel ingress ports from a second plurality of data communication ports of the network device, the first and second ingress ports being independent of one another;

writing the packet data to the memory using a multiplied clock signal operating at a multiplied clock speed that is greater than the clock speed for the network device;

reading out the data from the memory at the multiplied clock speed; and

providing the data to at least two egress modules of the packet processing pipeline at the clock speed for the network device,

wherein the multiplied clock signal is used to sample the network device clock signal to place timing domains of the multiplied clock signal and the network device clock signal in phase.

9. The method according to claim 8 , wherein the reading and writing are performed using a doubled clock speed that is double the clock speed for the network device.

10. The method according to claim 8 , wherein the reading comprises reading four output values pipelined together from the memory every clock cycle of the clock for the network device and the writing step comprises writing four input values pipelined together to the memory every clock cycle of the clock for the network device.

11. The method according to claim 10 , wherein the writing comprises writing four address, command and data components to the memory every clock cycle and the reading step comprises reading four address, command and data components from the memory every clock cycle for the network device.

12. The method according to claim 10 , wherein MMU comprises a series of flip-flops and the writing further comprises receiving each of the four input/output values at least one flip-flop, wherein the series of flip-flops is configured to operate in the multiplied clock signal timing domain.

13. The method according to claim 10 , wherein the reading is performed such that a setup and hold margin is created with the data in the multiplied clock signal timing domain to facilitate the capture of the data into the network device clock signal timing domain.

14. The method according to claim 8 , wherein the method is performed such that the method tolerates a jitter of one eighth of a clock cycle of the network device clock signal and still operates correctly.

15. An apparatus for processing packet data in a packet processing pipeline of a network device, the apparatus comprising:

a first plurality of data communication port means;

a second plurality of data communication port means;

first and second independent and parallel receiving means for receiving, from, respectively, the first plurality of data communication port means and the second plurality of data communication port means, data to be stored in a memory by a memory management unit (MMU) using a network device clock signal operating at a clock speed for the network device;

writing means for writing the data to the memory using a multiplied clock signal operating at a multiplied clock speed that is greater than the clock speed for the network device;

reading means for reading out the data from the memory at the multiplied clock speed; and

providing means for providing the data to two or more parallel egress modules of the packet processing pipeline network device at the clock speed for the network device;

wherein the multiplied clock signal is used to sample the network device clock signal to place timing domains of the multiplied clock signal and the network device clock signal in phase.

16. The apparatus according to claim 15 , wherein the reading and writing means are configured to use a doubled clock speed that is double the clock speed for the network device.

17. The apparatus device according to claim 15 , wherein the reading means comprises second reading means for reading four output values pipelined together from the memory every clock cycle of the clock for the network device and the writing means comprises second writing means for writing four input values pipelined together to the memory every clock cycle of the clock for the network device.

18. The apparatus according to claim 17 , wherein the second writing means comprises third writing means for writing four address, command and data components to the memory every clock cycle and the second reading means comprises third reading means for reading four address, command and data components from the memory every clock cycle.

19. The apparatus according to claim 17 , wherein the second writing means comprises a series of flip-flops and the series of flip-flop is configured to receive each of the four input/output values at least one flip-flop and to operate in the multiplied clock signal timing domain.

20. The apparatus according to claim 17 , wherein the second reading means is configured to create a setup and hold margin with the data in the multiplied clock signal timing domain to facilitate the capture of the data into the network device clock signal timing domain.