SRAM devices based on resonant tunneling
The present invention discloses a resonant tunneling device. Further, the present invention discloses a memory storage device utilizing a resonant tunneling barrier. Moreover, the present invention teaches an SRAM circuit utilizing a resonant tunneling device. Additionally, the present invention teaches an NROM and NAND device utilizing a resonant tunneling barrier.
1 . A SRAM circuit comprising:
a transistor having a source, gate and drain,
a bitline coupled to said source,
a wordline coupled to said gate, and
a resonant tunneling device coupled to said drain and a load.
2 . The circuit as claimed in claim 1 wherein said resonant tunneling device comprises:
a first bandgap,
a second bandgap, and
a third bandgap sandwiched between said first bandgap and said second bandgap;
wherein said first bandgap and said second bandgap are larger than said third bandgap.
3 . The device as claimed in claim 2 wherein said first bandgap consists essentially of one of SiO 2 and Al 3 O 4 .
4 . The device as claimed in claim 2 wherein said second bandgap consists essentially of one of SiO 2 and Al 3 O 4 .
5 . The device as claimed in claim 2 wherein said third bandgap consists essentially of one of poly-crystalline silicon, crystalline silicon, Pt, Ir, Ni, Ge, Be, Re, TaO, TaN, BaTiO, BaZrO, ZrO, HfO, TiN, Ti, ZrN, WN, Mo, MoN, and MoSi.
6 . The device as claimed in claim 3 wherein said second bandgap consists essentially of one of SiO 2 and Al 3 O 4 .
7 . The device as claimed in claim 6 wherein said third bandgap consists essentially of one of poly-crystalline silicon, crystalline silicon, Pt, Ir, Ni, Ge, Be, Re, TaO, TaN, BaTiO, BaZrO, ZrO, HfO, TiN, Ti, ZrN, WN, Mo, MoN, and MoSi.
8 . The circuit as claimed in claim 1 wherein said load consists essentially of one of a resistive load, current source, and resonant tunneling load.