SONOS memory with inversion bit-lines
View Patent ↗A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.
1. A method of operating a SONOS memory cell formed on a semiconductor substrate, comprising:
applying a respective bit-line gate bias on at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate, wherein the inversion bit-line forms one of drain and source regions of the SONOS memory cell;
applying a respective bias voltage on the inversion bit-line for affecting an amount of charge stored within a charge trapping material disposed between a bottom dielectric and a top dielectric during a program/erase of the SONOS memory cell; and
applying respective bias voltages on a word-line structure, a substrate, and the other of the drain and source regions of the SONOS memory cell during the program/erase of the SONOS memory cell,
wherein the bottom dielectric, the charge trapping material, and the top dielectric are stacked over the word-line structure formed in a region of the semiconductor substrate between the drain and source regions.
2. The method of claim 1 , further comprising:
applying a first bit-line gate bias on a first bit-line gate for inducing a first inversion bit-line that forms the source region within the semiconductor substrate;
applying a second bit-line gate bias on a second bit-line gate for inducing a second inversion bit-line that forms the drain region within the semiconductor substrate; and
applying a third bit-line gate bias on a third bit-line gate that is disposed between the first and second bit-line gates for inducing a conductive path from the first inversion bit-line to the second inversion bit-line, during source side injection programming.
3. The method of claim 2 , further comprising:
floating the first, second, and third bit-line gates; and
applying a negative voltage on the word-line structure formed on the top dielectric, for erasing charge from the charge trapping material.
4. The method of claim 3 , wherein the top dielectric is comprised of a high-k dielectric material having a dielectric constant higher than that of silicon dioxide (SiO 2 ).
5. The method of claim 2 , further comprising:
floating the first, second, and third bit-line gates; and
applying a positive voltage on the word-line structure formed on the top dielectric, for erasing charge from the charge trapping material.
6. The method of claim 5 , wherein the bottom dielectric is comprised of a high-k dielectric material having a dielectric constant higher than that of silicon dioxide (SiO 2 ).
7. The method of claim 1 , wherein the charge trapping material includes a plurality of charge trapping structures, with each charge trapping material structure electrically isolated and disposed along a side of a bit-line gate.
8. The method of claim 1 , wherein the bit-line gate is within a trench of the semiconductor substrate.
9. The method of claim 1 , wherein the word-line structure, that is adjacent the top dielectric, is within a trench of the semiconductor substrate.
10. The method of claim 1 , wherein at least one of the top dielectric, the charge trapping material, and the bottom dielectric is comprised of a respective high-k dielectric material having a dielectric constant higher than that of silicon dioxide (SiO 2 ).
11. The method of claim 1 , wherein the charge trapping material is a charge trapping structure that is electrically isolated and disposed along a side of a bit-line gate.
12. The method of claim 1 , wherein the charge trapping material includes a plurality of charge trapping structures, with each charge trapping structure electrically isolated and disposed along a side of a bit-line gate.
13. The method of claim 1 , further comprising:
applying a bias voltage to a contact junction formed outside of a core region for applying the bias voltage on the inversion bit-line.
14. The method of claim 1 , wherein the charge trapping material is comprised of a nano-crystal material.
15. The method of claim 1 , further comprising:
applying a respective bit-line gate bias on another bit-line gate for inducing another inversion bit-line that forms the other of the drain and source regions of the SONOS memory cell.