Image sensor having pinned floating diffusion diode
View Patent ↗The present invention provides an image sensor having a pinned floating diffusion region in addition to a pinned photodiode. The pinned floating diffusion region increases the capacity of the sensor to store charge, increases the dynamic range of the sensor and widens intra-scene intensity variation.
1. An imager integrated circuit comprising:
a doped layer formed in a substrate;
an array of pixel sensor cells formed in the doped layer, wherein at least one pixel sensor cell has a charge collection region and a photoconversion device;
the photoconversion device being a pinned photodiode and having a first pinning potential;
the charge collection region having a second pinning potential different than the first pinning potential and comprising a region of a first conductivity type at an upper surface of a region of a second conductivity type.
2. The imager according to claim 1 wherein the charge collection region is a floating diffusion region.
3. The imager according to claim 1 further comprising a storage capacitor coupled to the charge collection region.
4. The imager according to claim 1 wherein the imager is a CMOS imager.
5. A method of forming a pixel sensor cell comprising:
forming a photoconversion device, the photoconversion device being a pinned photodiode and configured to have a first pinning potential;
forming a charge collection region configured to have a second pinning potential different from the first pinning potential and to receive charges from the photoconversion device, the act of forming the charge collection region comprising forming a region of a first conductivity type at an upper surface of a region of a second conductivity type.
6. A method according to claim 5 further comprising forming a transfer transistor for transferring charge from said photoconversion device to the charge collection region.
7. The method according to claim 5 wherein the charge collection region is formed as a floating diffusion region.
8. The method according to claim 5 wherein the charge collection region is formed within a region of the first conductivity type.
9. The method according to claim 5 wherein the second conductivity type region is an n-type region, wherein the first conductivity type regions is a p+ type region formed within the n-type region.
10. The method according to claim 9 further comprising an n+type region within the n-type region.
11. The method according to claim 10 wherein said the n+type region is associated with a contact.
12. The method according to claim 10 wherein the n+ type region and the p+ type region are separated from one another by a portion of the n-type region.
13. The method according to claim 10 wherein the p+type region surrounds the n+ type region, the n+ type region extending into the n-type region.
14. The method according to claim 9 wherein the p+ type region is located adjacent to a transfer transistor gate.
15. The method according to claim 9 wherein the p+ type region does not contact a reset transistor gate channel region.
16. The method according to claim 5 further comprising an external storage capacitor electrically connected to the charge collection region.
17. The imager according to claim 1 further comprising signal processing circuitry formed in the substrate and electrically connected to the array for receiving and processing pixel signals representing an image acquired by the array and for providing output data representing the image.
18. The imager according to claim 1 wherein the doped layer is of the first conductivity type.
19. The imager according to claim 18 wherein the region of a first conductivity type has a higher dopant concentration than the doped layer.