Apparatus and method to reduce jitter in a phase locked loop
A circuit and method to reduce jitter and/or noise in a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) control signal is tapped and filtered to create a low-noise, filtered VCO control signal. The filtered and unfiltered control signals are individually weighted and then combined to create a modified VCO control signal which reduces the jitter and/or the noise by reducing an effect of VCO gain on the jitter and/or the noise.
1. A circuit that reduces jitter in a phase-locked loop (PLL), comprising:
a filter having an input and an output, wherein said filter is part of the PLL; and
a summation circuit coupled to said filter input and said filter output, wherein said summation circuit is configured to add a part of a filter output signal and a part of a filter input signal to provide a voltage controlled oscillator (VCO) control signal that reduces the jitter,
wherein said filter input is coupled to a loop filter having a resistor coupled to a capacitor via a node, wherein said filter input is coupled to said node.
2. The circuit of claim 1 , wherein the circuit is deposited on a substrate.
3. The circuit of claim 1 , wherein said filter includes a low pass filter.
4. The circuit of claim 3 , wherein said low pass filter includes:
an amplifier having a first input, a second input, and an output, wherein said amplifier first input is coupled to said filter input, further wherein said amplifier second input is coupled to said amplifier output;
a resistor coupled between said amplifier output and said filter output; and
a capacitor coupled between said filter output and ground.
5. The circuit of claim 1 , further comprising:
a first variable current source having an output coupled to a node and a control input coupled to said filter input; and
a second variable current source having an output coupled to said node and a control input coupled to said filter output;
wherein said node is coupled to a current-controlled oscillator.
6. The circuit of claim 5 , further including a mirror circuit coupled between said node and said current-controlled oscillator.
7. The circuit of claim 1 , further including a proportioning circuit coupled between said filter and said summation circuit, wherein said proportioning circuit weights said filter output signal and said filter input signal.
8. A method to reduce jitter in a phase-locked loop (PLL), comprising:
receiving a filter input signal;
filtering said filter input signal with a low-pass resistor-capacitor filter to produce a filter output signal;
adding said filter input signal with said filter output signal to produce a voltage controlled oscillator (VCO) control signal; and
controlling a VCO with said VCO control signal to reduce the jitter.
9. The method of claim 8 , wherein said filtering includes low-pass filtering.
10. The method of claim 8 , wherein said controlling includes varying a VCO control current at least in part with said filter output signal.
11. The method of claim 10 , wherein said controlling includes at least one of controlling a first voltage-controlled current source with said filter output signal to vary said VCO control current and controlling a second voltage-controlled current source with said filter input signal to vary said VCO control current.
12. The method of claim 10 , wherein said controlling includes mirroring said VCO control current.
13. The method of claim 8 , wherein said controlling includes altering a VCO output frequency with said VCO control signal.
14. The method of claim 8 , further comprising:
weighting said filter input signal by a first factor; and
weighting said filter output signal by a second factor.
15. The method of claim 8 , wherein said controlling includes:
multiplying said filter input signal by a first proportioning transconductance to create a first control current;
multiplying said filter output signal by a second proportioning transconductance to create a second control current; and
adding said first control current with said second control current to create a VCO control current;
wherein said VCO control current controls said VCO.
16. A circuit that reduces phase-locked loop (PLL) jitter, comprising:
means for receiving a filter input signal;
means for filtering said filter input signal to produce a filter output signal;
means for adding said filter input signal with said filter output signal to produce a voltage controlled oscillator (VCO) control signal; and
means for controlling a VCO with said VCO control signal to reduce the jitter.
17. The circuit of claim 16 , wherein said controlling means includes means for varying a VCO control current at least in part with said filter output signal.
18. The circuit of claim 16 , further comprising:
means for weighting said filter input signal by a first factor; and
means for weighting said filter output signal by a second factor.
19. The circuit of claim 16 , wherein said controlling means includes:
means for multiplying said filter input signal by a first proportioning transconductance to create a first control current;
means for multiplying said filter output signal by a second proportioning transconductance to create a second control current; and
means for adding said first control current and said second control current to create a VCO control current;
wherein said VCO control current controls said VCO.