Multiple input single output (MISO) amplifier having multiple transistors whose output voltages substantially equal the amplifier output voltage
Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.
1. A method comprising:
receiving an input clock at a frequency that corresponds to a desired output frequency;
receiving information;
generating two or more substantially constant envelope signals derived from the information; and
combining the two or more substantially constant envelope signals, comprising:
providing the two or more substantially constant envelope signals to a multiple input single output (MISO) device, the MISO device comprising two or more circuit branches each having one or more transistors, wherein an output voltage of each of the one or more transistors in the two or more circuit branches of the MISO device is substantially equal to an output voltage of the MISO device for all operational instances of time of the MISO device.
2. The method of claim 1 , wherein the MISO device comprises first and second branches, wherein a transistor of the first branch and a transistor of the second branch are bipolar junction transistors (BJTs).
3. The method of claim 2 , wherein the transistor of the first branch is coupled to the transistor of the second branch in a common collector node configuration.
4. The method of claim 2 , wherein the transistor of the first branch is an npn BJT and the transistor of the second branch is a pnp BJT.
5. The method of claim 1 , wherein the MISO device comprises first and second branches, wherein a transistor of the first branch and a transistor of the second branch are MOS transistors.
6. The method of claim 5 , wherein the transistor of the first branch is coupled to the transistor of the second branch in a common drain node configuration.
7. The method of claim 5 , wherein the transistor of the first branch is a an NMOS transistor and the transistor of the second branch is a PMOS transistor.
8. The method of claim 1 , wherein the information comprises an input signal and wherein an output signal of the MISO device is an amplified version of the input signal.
9. The method of claim 1 , wherein the MISO device comprises first and second branches, wherein a first transistor of the first branch is connected to a second transistor of the second branch via a collector or drain terminal of each of the first and second transistors.
10. An amplifier comprising:
an input module configured to generate two or more constant envelope signals based on received information and a received input clock frequency having a frequency that corresponds to a desired output frequency; and
a multiple input single output (MISO) device configured to receive the two or more constant envelope signals, wherein the MISO device includes two or more branches each having one or more transistors, wherein an output voltage of each of the one or more transistors in the two or more circuit branches of the MISO device is substantially equal to an output voltage of the MISO device for all operational instances of time of the MISO device.
11. The amplifier of claim 10 , wherein the MISO device comprises first and second branches, wherein a transistor of the first branch is coupled to a transistor of the second branch in a common collector node configuration.
12. The amplifier of claim 11 , wherein the transistor of the first branch is an npn bipolar junction transistor (BJT) and the transistor of the second branch is a pnp BJT.
13. The amplifier of claim 10 , wherein the MISO device comprises first and second branches, wherein a transistor of the first branch and a transistor of the second branch are MOS transistors.
14. The amplifier of claim 13 , wherein the transistor of the first branch is coupled to the transistor of the second branch in a common drain node configuration.
15. The amplifier of claim 13 , wherein the transistor of the first branch is an NMOS transistor and the transistor of the second branch is a PMOS transistor.
16. The amplifier of claim 10 , wherein the information comprises an input signal and wherein an output signal of the MISO device is an amplified version of the input signal.
17. The amplifier of claim 10 , wherein the MISO device comprises first and second branches, wherein a first transistor of the first branch is connected to a second transistor of the second branch via a collector or drain terminal of each of the first and second transistors.
18. A device comprising an amplifier, the amplifier comprising:
an input module configured to generate two or more constant envelope signals based on received information and a received input clock frequency having a frequency that corresponds to a desired output frequency; and
a multiple input single output (MISO) device configured to receive the two or more constant envelope signals, wherein the MISO device includes two or more branches each having one or more transistors, wherein an output voltage of each of the one or more transistors in the two or more circuit branches of the MISO device is substantially equal to an output voltage of the MISO device for all operational instances of time of the MISO device.