Pulse controller with dual latches
A pulse controller with dual latches includes a first latch unit and a second latch unit, in which two latch units are used to latch signal level for ensuring a sufficient conducting amount of the switching element in the rear end power output unit, and through a mutual interaction between the first and the second latch units, a complementary turning-on and turning-off situation therebetween is formed, and further, the signal from a trigger signal source and the feedback from the power output unit are employed to generate the duty cycle signal for the power output unit so as to replace the conventional pulse width modulation circuit.
1. A pulse controller with dual latches in which two sets of latch units are used to receive a signal from a trigger signal source and a feedback from a rear end power output unit so as to generate a duty cycle of the power output unit, the pulse controller comprising:
a first latch unit having a low level and a high level working states, wherein when the first latch unit is triggered, the original working state thereof is switched to one of the low level and the high level working states and maintained until being triggered again; and
a second latch unit having a low level and a high level working states, wherein the working states of the second latch unit and the first latch unit are different but switched at the same time so as to form a complementary relationship therebetween, and wherein when the second latch unit is triggered, the first latch unit is driven to release voltage so as to latch the output at low level, and when the second latch unit receives the signal form the trigger signal source and the feedback from the power output unit, the first latch unit is driven to latch or release voltage level, thereby the complementary relationship between the first and the second latch units forms a duty cycle with low and high levels for controlling the power output unit;
wherein a temperature compensating element is further included between the first and the second latch units.
2. The pulse controller with dual latches as claimed in claim 1 , wherein the temperature compensating element is a resistor.
3. The pulse controller with dual latches as claimed in claim 1 , wherein the trigger signal source generates an oscillating waveform signal of a linear voltage ramp waveform with potential difference.
4. The pulse controller with dual latches as claimed in claim 3 , wherein die second latch unit is triggered by the negative edge of the oscillating waveform signal of the linear voltage ramp waveform for releasing voltage level.
5. The pulse controller with dual latches as claimed in claim 1 , wherein the trigger signal source generates a square wave signal having high and low levels.
6. The pulse controller with dual latches as claimed in claim 5 , wherein the second latch unit is triggered by the positive and negative edges of the square wave signal to latch or release voltage level.
7. The pulse controller with dual latches as claimed in claim 1 , further comprising a plurality of capacitors for preventing noise interference at the front edges of signals from the trigger signal source and the power output unit.
8. The pulse controller with dual latches as claimed in claim 1 , wherein the trigger signal source is a timing signal source.