Method, apparatus and system providing a one-time programmable memory device
Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory devise having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.
1. A memory device, comprising:
a plurality of memory cells arranged in an array of rows and columns, at least one of the memory cells comprising:
a one-time programmable anti-fuse element;
a storage region for storing a charge related to the programmed state of the anti-fuse element, and
an amplifier transistor having a gate connected to the storage region for amplifying a signal from the storage region and providing the amplified signal as an output signal.
2. The memory device of claim 1 wherein the anti-fuse element is a MOSFET transistor.
3. The memory device of claim 1 wherein the anti-fuse element is a capacitor.
4. The memory device of claim 1 further comprising a column readout circuit for receiving the output signal from a column line of the array.
5. The memory device of claim 4 , wherein the readout circuit comprises:
a circuit for reading out the at least one memory cell as a reset state of the storage region and as a signal state of the storage region which is determined by the state of the anti-fuse element.
6. The memory device of claim 5 , wherein the readout circuit further comprises sample and hold circuitry for storing the reset state and signal state, and a differential amplifier for subtracting the signals stored in the sample and hold circuitry.
7. The memory device of claim 4 wherein the readout circuit comprises a sense amplifier.
8. The memory device of claim 4 wherein the readout circuit comprises a comparator.
9. The memory device of claim 4 wherein the readout circuit comprises a readout amplifier.
10. A memory device, comprising:
a plurality of memory cells arranged in an array of rows and columns, at least one of the memory cells comprising:
an anti-fuse element, having a first node coupled to a first voltage source line;
a first transistor having one source/drain terminal, coupled to a second node of the anti-fuse element, and a gate coupled to a second voltage line;
a second transistor having one source/drain terminal coupled to a bit line, a second source/drain terminal coupled to a second source/drain terminal of the first transistor, and a gate coupled to a word line;
a storage node between source/drain terminals of the first and second transistors;
a third transistor having a gate coupled to the storage node, for supplying an output signal; and
a fourth transistor, coupled to the third transistor, for selectively providing the output signal to a column line and having a gate coupled to a word read line.
11. The memory device of claim 10 wherein the anti-fuse element is a MOSFET transistor.
12. The memory device of claim 10 wherein the anti-fuse element is a capacitor.
13. The memory device of claim 10 , further comprising:
a first voltage source for supplying a first voltage to the first voltage source line; and
a second voltage source for supplying a second voltage to the second voltage line, wherein the second voltage is approximately one half of the first voltage.
14. The memory device of claim 10 further comprising a readout circuit for reading out the at least one memory cell.
15. The memory device of claim 14 , wherein the readout circuit comprises a readout amplifier coupled to the column line.
16. The memory device of claim 14 , wherein the readout circuit comprises a sense amplifier coupled to the column line.
17. The memory device of claim 14 , wherein the readout circuit comprises a comparator coupled to the column line.
18. The memory device of claim 14 wherein the readout circuit reads out a signal produced by said third transistor representing a reset state of the storage region and a signal representing a state of the storage region which is determined by the state of the anti-fuse element.
19. The memory device of claim 18 , wherein the readout circuit further comprises a first storage capacitor for storing the signal representing the reset state, a second storage capacitor for storing the signal representing the storage region state determined by the state of the anti-fuse element, and a differential amplifier for subtracting the signals stored on the capacitors.
20. A memory device, comprising:
a plurality of memory cells arranged in an array of rows and columns, at least one memory cell comprising:
a one-time programmable anti-fuse element, having a first node coupled to a first voltage source line;
a first transistor having one source/drain terminal coupled to a bit line and a gate coupled to a word line;
a storage node coupled between the source/drain terminal of the first transistor and the anti-fuse element;
a second transistor, having a gate coupled to the storage node for supplying an output signal; and
a third transistor, coupled to the second transistor, for providing the output signal to a column line and having a gate coupled to a word read line.
21. The memory device of claim 20 , wherein the anti-fuse element is a MOSFET.
22. The memory device of claim 20 , wherein the anti-fuse element is a capacitor.
23. The memory device of claim 20 , wherein the anti-fuse element is programmable by a first voltage which is less than or equal to 5V.
24. The memory device of claim 21 further comprising a readout circuit for reading out the at least one memory cell.
25. The memory device of claim 24 , wherein the readout circuit comprises a readout amplifier coupled to the column line.
26. The memory device of claim 24 , wherein the readout circuit comprises a sensor amplifier coupled to the column line.
27. The memory device of claim 24 , wherein the readout circuit comprises a comparator coupled to the column line.
28. The memory device of claim 24 wherein the readout circuit reads out a signal produced by the third transistor representing a reset state of the storage region and a signal representing a state of the storage region which is determined by the state of the anti-fuse element.
29. The memory device of claim 27 , wherein the readout circuit comprises a first storage capacitor for storing a signal representing the reset state, a second storage capacitor for storing the signal representing the storage region state determined by the state of the anti-fuse element, and a differential amplifier for subtracting the signals stored on the capacitors.
30. A memory cell, comprising:
a one-time programmable anti-fuse element, having a first node coupled to a line for receiving a common programming voltage;
a first transistor having one source/drain terminal coupled to a bit line and a gate coupled to a word line;
a storage node coupled between the source/drain terminal of the first transistor and the anti-fuse;
a second transistor, having a gate coupled to the storage node for supplying an output signal; and
a third transistor, coupled to the second transistor, for providing the output signal to an output line and having a gate coupled to a word read line.
31. The memory cell of claim 30 , further comprising
an anti-fuse element, having a first node coupled to a line for receiving a common programming voltage;
a first transistor having one source/drain terminal coupled to a bit line and a gate coupled to a word line;
a storage node coupled between the source/drain terminal of the first transistor and the anti-fuse;
a second transistor, having a gate coupled to the storage node for supplying an output signal;
a third transistor, coupled to the second transistor, for providing the output signal to an output line and having a gate coupled to a word read line; and
a fourth transistor coupled between the storage region and the anti-fuse, and having a gate coupled to a constant voltage line.
32. A system comprising:
a processor;
a memory device coupled to the processor, the memory device comprising a plurality of memory cells, at least one of the memory cells comprising:
a one-time programmable anti-fuse element;
an in-cell amplifier for detecting a signal produced by the programmed state of the anti-fuse element and providing an output signal on a column line representing that state;
a first node of the anti-fuse element coupled to a first voltage line;
a first transistor having one source/drain terminal coupled to a bit line, and a gate coupled to a word line;
a storage node, coupled between the source/drain terminal of the first transistor and the anti-fuse;
a second transistor, having a gate coupled to the storage node for supplying an output signal; and
a third transistor, coupled to the second transistor, for providing the output signal to the column line and having a gate coupled to a word read line.
33. The system of claim 32 , wherein the system is a camera system.
34. A system comprising:
a processor;
a memory device coupled to the processor, the memory device comprising a plurality of memory cells, at least one of the memory cells comprising:
a programmable anti-fuse element;
an in-cell amplifier for detecting a signal produced by the programmed state of the anti-fuse element and providing an output signal on a column line representing that state;
a first node of the anti-fuse element coupled to a first voltage line;
a first transistor having one source/drain terminal coupled to a bit line, and a gate coupled to a word line;
a storage node, coupled between the source/drain terminal of the first transistor and the anti-fuse element;
a second transistor, having a gate coupled to the storage node for supplying an output signal;
a third transistor, coupled to the second transistor, for providing the output signal to the column line and having a gate coupled to a word read line; and
a fourth transistor coupled between the storage region and the anti-fuse, coupled to a second node of the anti-fuse element, where a gate of the fourth transistor is coupled to a line for receiving a constant voltage.
35. The system of claim 34 , wherein the system is a camera system.