Method of fabricating SRAM device
View Patent ↗A method of fabricating an SRAM device is provided, by which a junction node area is stably secured in a 1T type SRAM device. The method includes forming first and second conductor patterns on a cell area of a semiconductor substrate and a third conductor pattern on a periphery area of the semiconductor substrate, stacking first to third insulating layers over the substrate, forming a spacer on a sidewall of the third conductor pattern in the exposed periphery area, removing the third insulating layer, and forming first and second spacers on sidewalls of the first and second conductor patterns.
1. An SRAM device, comprising:
first and second conductor patterns on a cell area of a semiconductor substrate and a third conductor pattern on a periphery area of the semiconductor substrate;
first and second spacers, each comprising at least two insulating layers, on sidewalls of the first and second conductor patterns; and
a third spacer, comprising at least three insulating layers including said at least two insulating layers, on a sidewall of the third conductor pattern,
wherein both of the first and second spacers have at least one less insulating layer than the third spacer.
2. The device of claim 1 , wherein the first insulating layer has a thickness of 150˜250 Å.
3. The device of claim 1 , wherein the second insulating layer has a thickness of 450˜550 Å.
4. The device of claim 1 , wherein the third insulating layer has a thickness of 250˜350 Å.
5. The device of claim 1 , wherein the first conductor pattern comprises a gate electrode of a transistor.
6. The device of claim 1 , wherein the second conductor pattern comprises an upper electrode of a capacitor.
7. The device of claim 1 , wherein the first and third insulating layers comprise an oxide.
8. The device of claim 1 , wherein the second insulating layer comprises a nitride.
9. The device of claim 1 , further comprising LDD ion implant regions in active areas of the substrate, aligned with the first, second and third conductor patterns.
10. The device of claim 1 , further comprising source/drain ion implant regions in active areas of the substrate, aligned with the first, second and third spacers.