IP Library Granted Patent US 7,425,863
Granted Patent B2
US 7,425,863 · App. 11/604,194 · Granted Sep 16, 2008

Tuneable filters using operational amplifiers

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Quick Facts
Patent No.
US 7,425,863
App. No.
11/604,194
Granted
Sep 16, 2008
Kind
B2
Abstract

A low pass filter includes a switchable resistor bank, a gain stage, and a capacitor bank. The resistors and capacitors switched into the circuit determine a cutoff frequency of the low pass filter. Frequency programmability may be obtained using the switchable resistor bank implemented as a parallel bank of binary weighted resistors. Further frequency programmability may be obtained using the switchable capacitor bank in conjunction with the switchable resistor bank. The resistor and capacitor processes in a semiconductor wafer are sufficiently accurate and repeatable so as to minimize any necessary calibration.

Claims (45)

1. A low pass filter, comprising:

a first stage including a first switchable resistor bank, the first gain stage having an input coupled to the first switchable resistor bank, and a first feedback capacitor, wherein the first feedback capacitor is coupled between the input of the first gain stage and an output of the first gain stage;

a boost stage including a second switchable resistor bank coupled to the output of the first gain stage;

a second stage coupled to the boost stage including a third switchable resistor bank, the second gain stage having an input coupled to the third switchable resistor bank, and a second feedback capacitor, wherein the second feedback capacitor is coupled between the second switchable resistor bank and an output of the second gain stage; and

a third stage coupled to the boost stage including a fourth switchable resistor bank, the third gain stage having an input coupled to the fourth switchable resistor bank, and a third feedback capacitor, wherein the third feedback capacitor is coupled between the fourth switchable resistor bank and an output of the third gain stage and to the second switchable resistor bank.

2. The low pass filter of claim 1 , further comprising:

a fourth stage including a fifth switchable resistor bank, the fourth gain stage having an input coupled to the fifth switchable resistor bank and an output coupled to the first switchable resistor bank, and a fourth feedback capacitor, wherein the fourth feedback capacitor is coupled between the input of the fourth gain stage and the output of the fourth gain stage.

3. The low pass filter of claim 2 , wherein the first, second, third, fourth, and fifth switchable resistor banks further comprise:

a plurality of resistors coupled to a common input and to a plurality of switches, wherein each switch is coupled to a corresponding resistor in the plurality of resistors.

4. The low pass filter of claim 2 , wherein the first, the second, the third, and the fourth stages further comprise:

a switchable capacitor bank coupled between the input of the gain stage and the output of the gain stage.

5. The low pass filter of claim 4 , wherein the switchable capacitor bank further comprises:

a plurality of capacitors coupled to a common input and to a plurality of switches, wherein each switch is coupled to a corresponding capacitor in the plurality of capacitors.

6. The low pass filter of claim 1 , wherein the first and the second stages further comprise:

a first feedback resistor coupled between the input of first the gain stage and the output of the first gain stage; and

a second feedback resistor coupled between the input of the second gain stage and the output of the second gain stage.

7. The low pass filter of claim 6 , wherein the feedback resistor further comprises:

a plurality of resistors coupled to a common input and to a plurality of switches, wherein each switch is coupled to a corresponding resistor in the plurality of resistors.

8. The low pass filter of claim 2 , further comprising:

a first inversion resistor coupled between the output of the first gain stage and the input of the third gain stage; and

a second inversion resistor coupled between the output of the second gain stage and the input of the fourth gain stage.

9. The low pass filter of claim 8 , wherein the first and the second inversion resistors further comprise:

a plurality of resistors coupled to a common input and to a plurality of switches, wherein each switch is coupled to a corresponding resistor in the plurality of resistors.

10. A low pass filter, comprising:

a first stage including a first switchable resistor bank, the first gain stage having an input coupled to the first switchable resistor bank and an output coupled to a second switchable resistor bank, and a first feedback capacitor coupled between the input of the first gain stage and the output of the first gain stage;

a second stage including the second switchable resistor bank, the second gain stage having an input coupled to the second switchable resistor bank and an output coupled to a third switchable resistor bank, and a second feedback capacitor coupled between the input of the second gain stage and the output of the second gain stage;

a boost stage including a fourth switchable resistor bank coupled to the output of the second gain stage;

a third stage including the third switchable resistor bank, the third gain stage having an input coupled to the third switchable resistor bank and an output coupled to a fifth switchable resistor bank, and a third feedback capacitor coupled between the input of the third gain stage and the output of the third gain stage; and

a fourth stage including the fifth switchable resistor bank the fourth gain stage having an input coupled to the fifth switchable resistor bank and to an output of the boost stage, and a fourth feedback capacitor coupled between the input of the fourth gain stage and an output of the fourth gain stage.

11. The low pass filter of claim 10 , wherein the first, second, third, fourth, and fifth switchable resistor banks further comprise:

a plurality of resistors coupled to a common input and to a plurality of switches, wherein each switch is coupled to a corresponding resistor in the plurality of resistors.

12. The low pass filter of claim 10 , wherein the first, the second, the third, and the fourth stages further comprise:

a switchable capacitor bank coupled between the input of the gain stage and the output of the gain stage.

13. The low pass filter of claim 12 , wherein the switchable capacitor bank further comprises:

a plurality of capacitors coupled to a common input and to a plurality of switches, wherein each switch is coupled to a corresponding capacitor in the plurality of capacitors.

14. The low pass filter of claim 10 , wherein the second and the fourth stages further comprise:

a first feedback resistor coupled between the input of the second gain stage and the output of the second gain stage; and a

a second feedback resistor coupled between the input of the fourth gain stage and the output of the fourth gain stage.

15. The low pass filter of claim 14 , wherein the feedback resistor further comprises:

a plurality of resistors coupled to a common input and to a plurality of switches, wherein each switch is coupled to a corresponding resistor in the plurality of resistors.

16. The low pass filter of claim 10 , further comprising:

a first inversion resistor coupled between the output of the second gain stage and the input of the first gain stage; and

a second inversion resistor coupled between the output of the fourth gain stage and the input of the third gain stage.

17. The low pass filter of claim 16 , wherein the first and the second inversion resistors further comprise:

a plurality of resistors coupled to a common input and to a plurality of switches, wherein each switch is coupled to a corresponding resistor in the plurality of resistors.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2006
From: GATTA, FRANCESCO; RADHAMOHAN, RAJESHMOHAN
To: BROADCOM CORPORATION
Reel/Frame 018643/0524 →