An EEPROM having a nonvolatile memory cell is provided. The nonvolatile memory cell has a first MOS transistor and a second MOS transistor. The first MOS transistor and the second MOS transistor have a gate electrode in common, the gate electrode being a floating gate electrically isolated from a surrounding circuitry. The first MOS transistor and the second MOS transistor are of a same conductivity type.
1. An EEPROM having a nonvolatile memory cell, said nonvolatile memory cell comprising:
a first MOS transistor;
a second MOS transistor;
a floating well formed of a first conductivity type;
wherein said first MOS transistor and said second MOS transistor comprise a floating gate electrode in common, and said first MOS transistor and said second MOS transistor are of a same conductivity type;
wherein the first MOS transistor and the second MOS transistor are associated with a second well; and
wherein in data reading, a reading potential is applied to said second MOS transistor, a first potential is applied to a source and P-well of the first MOS transistor, and a second potential is applied to a drain of the first MOS transistor is an accumulation mode and the second MOS transistor is in an inversion mode.
2. The EEPROM according to claim 1 ,
wherein said first MOS transistor is formed on a first well, the first well formed on the floating well, in a substrate, and said second MOS transistor is formed on a second well, the second well formed on the floating well, in said substrate,
wherein both of said first MOS transistor and said second MOS transistor comprise the first conductivity type, while both of said first well and said second well comprise a second conductivity type opposite to said first conductivity type.
3. The EEPROM according to claim 1 , wherein the first conductivity type comprises an N-type, and
wherein the second conductivity type comprises a P-type.
4. The EEPROM according to claim 1 , wherein in data erasing, a first potential is applied to the floating gate, an erasing potential is applied to said first MOS transistor, a third potential is applied to the second MOS transistor.
5. The EEPROM according to claim 4 , wherein in the data erasing, the first MOS transistor is an accumulation mode and the second MOS transistor is in an inversion mode.
6. The EEPROM according to claim 1 , wherein in data programming, a first potential is applied to the floating gate, a programming potential is applied to said first MOS transistor, a third potential is applied to the second MOS transistor.
7. The EEPROM according to claim 6 , wherein in the data programming, the first MOS transistor is an inversion mode and the second MOS transistor is in an accumulation mode.
8. The EEPROM according to claim 1 , wherein a status of the first MOS transistor is detected to determine whether the first MOS transistor is on or off.
9. The EEPROM according to claim 1 , wherein a potential state of the floating gate corresponds to stored data.
10. The EEPROM according to claim 1 , wherein the first MOS transistor comprises a read transistor.
11. The EEPROM according to claim 1 , wherein the second MOS transistor comprises a Fowler-Nordheim (FN) tunneling transistor.
12. An EEPROM having a nonvolatile memory cell, said nonvolatile memory cell comprising:
a first MOS transistor;
a second MOS transistor; and
a floating well formed of a first conductivity type,
wherein said first MOS transistor and said second MOS transistor comprise a floating gate electrode in common, and said first MOS transistor and said second MOS transistor are of a same conductivity type, and
wherein said first MOS transistor is formed on a first well, the first well formed on the floating well, in a substrate, and said second MOS transistor is formed on a second well, the second well formed on the floating well, in said substrate,
wherein both of said first MOS transistor and said second MOS transistor comprise the first conductivity type, while both of said first well and said second well comprise a second conductivity type opposite to said first conductivity type,
wherein in data programming and erasing, a first potential is applied to said first well, a source and a drain of said first MOS transistor, and a second potential different from said first potential by a predetermined potential difference is applied to said second well, a source and a drain of said second MOS transistor, such that charge injection and ejection with respect to said floating gate electrode occur through a gate insulating film of said second MOS transistor.
13. The EEPROM according to claim 12 ,
wherein a MOS capacitance of said second MOS transistor is smaller than that of said first MOS transistor.
14. The EEPROM according to claim 12 ,
wherein in data reading, a potential state of said floating gate electrode is detected by using said first MOS transistor.
15. The EEPROM according to claim 13 ,
wherein in data reading, a potential state of said floating gate electrode is detected by using said first MOS transistor.
16. The EEPROM according to claim 12 ,
wherein said floating gate electrode is formed of a single-layer polysilicon.
17. An EEPROM having a nonvolatile memory cell, said nonvolatile memory cell comprising:
a semiconductor substrate of a first conductivity;
a floating well of a second conductivity formed on said substrate;
a first well of said first conductivity;
a first diffusion layer of said first conductivity formed on said first well, said first diffusion layer extending along a first line;
a second diffusion layer of said second conductivity formed on said first well, said second diffusion layer extending along a second line in parallel with said first line;
a third diffusion layer of said second conductivity formed on said first well, said third diffusion layer extending along a third line in parallel with said first line, none of said first to third line overlapping with one another;
a floating gate formed on said first well between said second and third diffusion layers to constitute a MOS transistor having said second diffusion layer as a source and said third diffusion layer as a drain, said floating gate extending along a forth line in parallel with said first line;
a second well of said first conductivity which is smaller than said first well;
a fourth diffusion layer of said first conductivity formed on said second well, said fourth diffusion layer being arranged on said first line;
a fifth diffusion layer of said second conductivity formed on said second well, said fifth diffusion layer being arranged on said second line and smaller than said second diffusion layer; and
a sixth diffusion layer of said second conductivity formed on said second well, said sixth diffusion layer being arranged on said third line and smaller than said third diffusion layer,
wherein said floating gate extends on said second well between said fifth and sixth diffusion layers to constitute a MOS transistor having said fifth diffusion layer as one of source and drain and said third diffusion layer as the other of source and drain.