Transistor structure with high input impedance and high current capability
View Patent ↗An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.
1. An integrated transistor device comprising:
a chip of semiconductor material; an electrical-insulation region delimiting an active area in said chip;
a bipolar transistor formed in said active area and including:
a collector region;
a bipolar base region contiguous to said collector region; and
an emitter region accommodated in said bipolar base region; and
a MOSFET contiguous with the bipolar transistor and including:
a source region, arranged at a distance from said bipolar base region;
a drain region;
a channel region arranged between said source and drain regions; and
an insulated-gate region that extends on top of said active area and on top of said channel region; wherein said bipolar base region is contiguous with a first side of the drain region and forms, with the drain region, a common base structure shared by said bipolar transistor and said MOSFET, wherein said common base structure comprises a LDD drain region surrounding said drain region at a bottom and on a second side thereof facing said channel region, said LDD drain region being formed as a continuation of said bipolar base region, thereby said drain region is surrounded at the first and second sides and at the bottom by said LDD drain region and said bipolar base region.
2. The integrated transistor device of claim 1 , wherein said bipolar transistor is a vertical transistor, and said collector region extends underneath said bipolar base region and said emitter region.
3. The integrated transistor device of claim 1 , wherein said emitter region and drain region are spaced from one another by a surface portion of said bipolar base region and a protection region of insulating material extends on top of said active area, vertically aligned to said surface portion of said bipolar base region, the protection region being thicker than a gate insulation layer that insulates the insulated-gate region from the channel region.
4. The integrated transistor device of claim 1 , wherein said active area further accommodates a well region contiguous and electrically connected to said collector region.
5. The integrated transistor device of claim 4 , wherein said collector region is a buried region that contacts and extends underneath the bipolar base region, the collector region and bipolar base region both contacting a same side of the well region.
6. The integrated transistor device of claim 4 , wherein said chip comprises a substrate; an epitaxial region, arranged on top of said substrate and
having a first conductivity type and a first doping level; and an LDD source region, surrounding said source region at the bottom and on the side thereof facing said channel region; wherein said well region is arranged on top of said epitaxial region and has said first conductivity type and a second doping level, higher than said first doping level; said LDD source and drain regions have a second conductivity type and a third doping level; said source and drain regions have said second conductivity type and a fourth doping level, higher than said third doping level; said collector region extends on top of said substrate, alongside said epitaxial region and said well region, and has said first conductivity type and a fifth doping level, higher than said first and second levels of doping; said bipolar base region extends directly on top of said collector region, next to said drain region, and has said second conductivity type and a sixth doping level, of the same order of magnitude as said third doping level; said emitter region has said first conductivity type and a seventh doping level, of the same order of magnitude as said fourth doping level.
7. The integrated transistor device of claim 6 , wherein said source, drain, emitter and gate regions are silicided.
8. The integrated transistor device of claim 1 , wherein said bipolar transistor is a PNP transistor and said MOSFET is an N-channel MOSFET.
9. The integrated transistor device of claim 1 , wherein said integrated transistor device has a “split” gate structure, said active area having a strip shape and accommodating a further drain region formed in said common base structure, on a side of said emitter region opposite to said drain region of said integrated transistor device, said active area moreover accommodating a sequence of further MOSFETs arranged on the two sides of each bipolar transistor.
10. The integrated transistor device of claim 1 , wherein said bipolar transistor is an NPN transistor and said MOSFET is a P-channel MOSFET.
11. A phase change memory array, comprising:
a plurality of memory cells arranged in rows and columns and each including a selection element and a memory element, wherein said selection element comprises an integrated transistor device that includes:
an electrical-insulation region delimiting an active area in a chip of semiconductor material;
a bipolar transistor formed in said active area and including:
a collector region;
a bipolar base region contiguous to said collector region; and
an emitter region accommodated in said bipolar base region; and
a MOSFET contiguous with the bipolar transistor and including:
a source region, arranged at a distance from said bipolar base region;
a drain region;
a channel region arranged between said source and drain regions; and
an insulated-gate region that extends on top of said active area and on top of said channel region; wherein said bipolar base region is contiguous with a first side of the drain region and forms, with the drain region, a common base structure shared by said bipolar transistor and said MOSFET, wherein said common base structure comprises a LDD drain region surrounding said drain region at a bottom and on a second side thereof facing said channel region, said LDD drain region being formed as a continuation of said bipolar base region, thereby said drain region is surrounded at the first and second sides and at the bottom by said LDD drain region and said bipolar base region.
12. The phase change memory array of claim 11 , wherein said emitter region and drain region are spaced from one another by a surface portion of said bipolar base region and a protection region of insulating material extends on top of said active area, vertically aligned to said surface portion of said bipolar base region, the protection region being thicker than a gate insulation layer that insulates the insulated-gate region from the channel region.
13. The phase change memory array of claim 11 , wherein said active area further accommodates a well region contiguous and electrically connected to said collector region:
14. The phase change memory array of claim 13 , wherein said collector region is a buried region that contacts and extends underneath the bipolar base region, the collector region and bipolar base region both contacting a same side of the well region.