Semiconductor memory device
View Patent ↗A semiconductor memory device includes plates accessed by different row addresses and a sense amplifier column between the adjacent plates. The sense amplifier column is a mixture of configurations, one in which one of the pair of bit lines is twisted, and another in which neither of the pair of bit lines is twisted. If an address analysis indicates that there is an access through an input/output wiring, input/output data is not inverted. If the address analysis indicates that there is an access through another input/output wiring and that it is an access to a plate, the input/output data is not inverted, while if it is an access to another plate, the input/output data is inverted.
1. A semiconductor memory device comprising:
a first pair of bit lines including a non-inverted bit line and an inverted bit line that can be selected by a row address in a first range;
a second pair of bit lines including a non-inverted bit line and an inverted bit line that can be selected by a row address in a second range that is not overlapping the first range;
a sense amplifier provided to be common to the first pair of bit lines and the second pair of bit lines; and
an address-data-topology correcting unit supplying write data and outputting read data to/from the first pair of bit lines without inverting and supplying write data and outputting read data to/from the second pair of bit lines with inverting, wherein
a positional relationship between the non-inverted bit line and the inverted bit line in the first pair of bit lines is opposite to a positional relationship between the non-inverted bit line and the inverted bit line in the second pair of bit lines.
2. The semiconductor memory device as claimed in claim 1 , wherein at least one of the number of memory cells connected to the first pair of bit lines and the number of memory cells connected to the second pair of bit lines differs from the number expressed by the n th power of 2.
3. The semiconductor memory device as claimed in claim 2 , wherein both the number of memory cells connected to the first pair of bit lines and the number of memory cells connected to the second pair of bit lines differ from the number expressed by the n th power of 2.
4. The semiconductor memory device as claimed in claim 1 , wherein the number of memory cells connected to the first pair of bit lines differs from the number of memory cells connected to the second pair of bit lines.
5. The semiconductor memory device as claimed in claim 1 , wherein a lowest row address of a memory cell among memory cells connected to the first pair of bit lines differs from a lowest row address of a memory cell among memory cells connected to the second pair of bit lines in a logic value by two bits or more.
6. The semiconductor memory device as claimed in claim 1 , wherein the first pair of bit lines and the second pair of bit lines belong to different plates from each other.