Semiconductor integrated circuit and method of manufacturing the same
Conventional capacitors constituted of a FET incur degradation in frequency response. A semiconductor integrated circuit includes a semiconductor substrate, an N-type FET, a P-type FET, and capacitors. The N-type FET includes N-type impurity diffusion layers, a P-type impurity-implanted region, a gate insulating layer, and a gate electrode. The P-type FET includes P-type impurity diffusion layers, an N-type impurity-implanted region, a gate insulating layer, and a gate electrode. The capacitor includes N-type impurity diffusion layers, an N-type impurity-implanted region, a capacitance insulating layer, and an upper electrode. The capacitor includes P-type impurity diffusion layers, a P-type impurity-implanted region, a capacitance insulating layer, and an upper electrode.
1. A semiconductor integrated circuit, comprising:
a semiconductor substrate, a field effect transistor, and a capacitor;
wherein the field effect transistor includes:
a first impurity diffusion layer of a first conductive type provided in the semiconductor substrate and acting as a source/drain region,
a first impurity-implanted region of a second conductive type provided in the semiconductor substrate and adjacent to the first impurity diffusion layer, and acting as a channel region,
a gate insulating layer provided on the first impurity-implanted region in the semiconductor substrate, and
a gate electrode provided on the gate insulating layer; and
the capacitor includes:
a second impurity diffusion layer of the first or the second conductive type provided in the semiconductor substrate,
a second impurity-implanted region of the same conductive type as the second impurity diffusion layer, provided in the semiconductor substrate and adjacent to the second impurity diffusion layer, and acting as a lower electrode,
a capacitance insulating layer provided on the second impurity-implanted region of the semiconductor substrate, and
an upper electrode provided on the capacitance insulating layer.
2. The semiconductor integrated circuit according to claim 1 ,
wherein said second impurity diffusion layer and said second impurity-implanted region are located in a well region provided in said semiconductor substrate; and
said well region is of the same conductive type as said second impurity diffusion layer.
3. The semiconductor integrated circuit according to claim 1 ,
wherein a conductive type of said second impurity diffusion layer is said first conductive type; and
said second impurity diffusion layer has generally the same impurity concentration profile as said first impurity diffusion layer.
4. The semiconductor integrated circuit according to claim 1 ,
wherein a conductive type of said second impurity diffusion layer is said second conductive type; and
said second impurity-implanted region has generally the same impurity concentration profile as said first impurity-implanted region.
5. The semiconductor integrated circuit according to claim 1 ,
wherein said capacitance insulating layer is constituted of an identical material to said gate insulating layer; and
said capacitance insulating layer has generally the same thickness as said gate insulating layer.
6. The semiconductor integrated circuit according to claim 1 ,
wherein said upper electrode is constituted of an identical material to said gate electrode; and
said upper electrode has generally the same thickness as said gate electrode.
7. The semiconductor integrated circuit according to claim 1 ,
wherein said capacitor is a decoupling capacitance provided between a power source and a ground.
8. The semiconductor integrated circuit according to claim 7 ,
wherein said capacitor is a fill-cell capacitance.
9. The semiconductor integrated circuit according to claim 1 ,
wherein said capacitor has a variable capacitance.
10. A method of manufacturing a semiconductor integrated circuit including a semiconductor substrate, a field effect transistor and a capacitor, comprising:
forming a first impurity diffusion layer of a first conductive type in the semiconductor substrate, thus constituting a source/drain region;
forming a first impurity-implanted region of a second conductive type in the semiconductor substrate and adjacent to the first impurity diffusion layer, thus constituting a channel region;
forming a gate insulating layer on the first impurity-implanted region in the semiconductor substrate;
forming a gate electrode on the gate insulating layer;
forming a second impurity diffusion layer of the first or the second conductive type in the semiconductor substrate;
forming a second impurity-implanted region of the same conductive type as the second impurity diffusion layer, in the semiconductor substrate and adjacent to the second impurity diffusion layer, thus constituting a lower electrode;
forming a capacitance insulating layer on the second impurity-implanted region of the semiconductor substrate; and
forming an upper electrode on the capacitance insulating layer.
11. The method according to claim 10 ,
wherein said forming a second impurity diffusion layer includes forming said second impurity diffusion layer in said first conductive type; and
said forming a first impurity diffusion layer and said forming a second impurity diffusion layer are executed at a time.
12. The method according to claim 10 ,
wherein said forming a second impurity diffusion layer includes forming said second impurity diffusion layer in said second conductive type; and
said forming a first impurity-implanted region and said forming a second impurity-implanted region are executed at a time.
13. The method according to claim 10 ,
wherein said forming a gate insulating layer and said forming a capacitance insulating layer are executed at a time.
14. The method according to claim 10 ,
wherein said forming a gate electrode and said forming an upper electrode are executed at a time.