System-on-chip with shield rings for shielding functional blocks therein from electromagnetic interference
View Patent ↗A system-on-chip (SoC) that is immune to electromagnetic interference has block shield rings fabricated therein. The SoC includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated circuit from electromagnetic interference. The EMI shield ring is grounded and includes a metal rampart consisting of multi-layer metals and vias. A pickup diffusion is connected to the metal rampart. In one embodiment, the memory block is also shielded.
1. A shield structure in a chip, comprising a first rampart consisting of a plurality of metal layers and a plurality of via layers, said first rampart having a first serpentine connection channel which comprises at least two sidewalls and extends from one side of said first rampart to the other in a serpentine manner, wherein said shield structure shields a pre-selected region of said chip, and wherein at least one serpentine signal line passes through said first serpentine connection channel.
2. The shield structure in a chip according to claim 1 wherein said first rampart is connected to a pickup diffusion implanted into a substrate.
3. The shield structure in a chip according to claim 2 wherein said substrate is a silicon-on-insulator (SOI) substrate.
4. The shield structure in a chip according to claim 1 wherein said first serpentine connection channel is an analog/digital (A/D) connection channel that allows digital-to-analog communication.
5. The shield structure in a chip according to claim 1 wherein said first rampart is grounded.
6. The shield structure in a chip according to claim 1 further comprising a second rampart having a second connection window that is not aligned with said first serpentine connection channel.
7. The shield structure in a chip according to claim 6 wherein said first serpentine connection channel and said second connection window are at different levels.
8. The shield structure in a chip according to claim 1 wherein said first rampart is two-side rampart and is connected to a closed seal ring that is disposed along perimeter of said chip.
9. The shield structure in a chip according to claim 1 wherein said chip is a system-on-chip chip.
10. The shield structure in a chip according to claim 1 wherein said pre-selected region is an on-chip memory block.
11. The shield structure in a chip according to claim 1 wherein said pre-selected region is an analog/mixed-signal block.
12. The shield structure in a chip according to claim 1 further comprising a complementary shield ring surrounding area of said chip other than said pre-selected region, wherein said complementary shield ring does not contact said first rampart.
13. A shield structure in a chip, comprising a first rampart consisting of a plurality of metal layers and a plurality of via layers, said first rampart having a first connection window, wherein said shield structure shields a pre-selected region of said chip, wherein at least one serpentine signal line passes through said first connection window and wherein said first rampart is two-side rampart and is connected to a closed seal ring that is disposed along perimeter of said chip.
14. A shield structure in a chip, comprising:
a first rampart consisting of a plurality of metal layers and a plurality of via layers, said first rampart having a first connection window, wherein said shield structure shields a pre-selected region of said chip, wherein at least one serpentine signal line passes through said first connection window; and
a complementary shield ring surrounding area of said chip other than said pre-selected region, wherein said complementary shield ring does not contact said first rampart.