Semiconductor device and method of manufacturing the same
View Patent ↗Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor device may include an LDD which may include a space having a first width and may be formed in a semiconductor substrate, a channel area which may be formed in the semiconductor substrate within a space having a first width, a gate insulating layer which has a width wider than the first width and may be formed on an upper side of the channel area on the semiconductor substrate, a gate which may be formed with the first width on the gate insulating layer, and a spacer including a first spacer formed at both sides of the gate insulating layer and a second spacer formed at sidewalls of the gate.
1. A method comprising:
sequentially forming an oxide layer and a nitride layer on an upper part of a semiconductor substrate;
forming a lightly doped drain (LDD) in the semiconductor substrate through an ion implantation process using a first mask layer having a first hole pattern;
forming a channel area in a center of the LDD having a width narrower than the first hole pattern using the nitride layer which is etched to remove the width narrower than a width of the first hole pattern;
selectively removing the oxide layer of the channel area through an etching process using the etched nitride layer;
forming a gate insulating layer in an area where the oxide layer was removed; and
forming a gate over the gate insulating layer and within the etched nitride layer,
wherein forming the channel area in the center of the LDD comprises:
forming a second mask layer having a second hole pattern on an upper part of the nitride layer, the second hole pattern having a width narrower than the width of the first hole pattern;
removing the second mask layer after selectively etching the nitride layer using the second mask layer; and
implanting ions having a conductive type opposite of a conductive type of ions used to form the LDD using the etched nitride layer as a mask.
2. The method of claim 1 , further comprising forming a spacer using a third mask having a width narrower than the width of the first hole pattern and wider than the width of the second hole pattern.
3. The method of claim 2 , wherein forming the spacer comprises:
gap-filling the gate insulating layer and the etched nitride layer with a conductive layer to form the gate;
forming a gap-filled gate on the gate insulating layer and the etched nitride layer by planarizing the conductive layer;
forming the third mask layer, having the width narrower than the width of the first hole pattern and wider than the width of the second hole pattern;
selectively etching the nitride layer and the oxide layer through an etching process using the third mask layer; and
removing the third mask layer.