IP Library Granted Patent US 8,130,005
Granted Patent B2
US 8,130,005 · App. 11/610,925 · Granted Mar 6, 2012

Electrical guard structures for protecting a signal trace from electrical interference

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Quick Facts
Patent No.
US 8,130,005
App. No.
11/610,925
Granted
Mar 6, 2012
Kind
B2
Abstract

A method of fabricating a guard structure can include depositing an insulating material over at least a portion of electrical signal conductors disposed on a component of a probe card assembly, and depositing an electrically conductive material onto the insulating material and at least a portion of electrical guard conductors disposed on the component of the probe card assembly. Each signal conductor can be disposed between a pair of the guard conductors. The probe card assembly can include a plurality of probes disposed to contact an electronic device to be tested. The signal conductors can be part of electrical paths within the probe card assembly to the probes.

Claims (39)

1. A probe card assembly comprising:

a plurality of probes disposed to contact an electronic device to be tested;

a substrate;

an electrical signal conductor disposed on the substrate, the signal conductor being part of an electrical path to one of the probes;

a pair of electrically conductive guard conductors disposed on the substrate, wherein the signal conductor is disposed between the pair of the guard conductors;

insulating material disposed outside of the substrate and on the signal conductor; and

a layer of electrically conductive material disposed outside of the substrate and on the insulating material and electrically connected to the guard conductors.

2. The probe card assembly of claim 1 , wherein:

the insulating material is also disposed on the guard conductors;

the insulating material comprises holes to the guard conductors; and

the layer of electrically conductive material is electrically connected to the guard conductors through the holes.

3. The probe card assembly of claim 2 , wherein the electrically conductive material fills the holes.

4. The probe card assembly of claim 2 , wherein:

the insulating material is disposed on less than an entire portion of the signal conductor and less than an entire portion of the guard conductors; and

the electrically conductive material is disposed on less than an entire surface of the insulating material.

5. The probe card assembly of claim 1 further comprising:

a plurality of electrically conductive signal conductors disposed on the substrate, the signal conductors being part of electrical paths to ones of the probes; and

a plurality of electrically conductive guard conductors disposed on the substrate, wherein ones of the signal conductors are disposed between pairs of the guard conductors,

wherein the insulating material is disposed on the signal conductors, and

the electrically conductive material disposed on the insulating material is electrically connected to the guard conductors.

6. The probe card assembly of claim 5 further comprising:

wherein the insulating material is also disposed on the guard conductors and comprises holes to the guard conductors, and

the electrically conductive material is electrically connected to the guard conductors through the holes.

7. The probe card assembly of claim 5 further comprising an electrical interface to a tester, wherein the conductive signal conductors are part of electrical paths between the electrical interface and ones of the probes.

8. The probe card assembly of claim 5 , wherein ones of the probes are attached to the substrate.

9. The probe card assembly of claim 5 , wherein ones of the signal conductors are connectable to a source of test signals for testing the electronic device.

10. The probe card assembly of claim 5 , wherein at least one of the conductive material and the guard conductors are connectable to a connection to ground voltage potential.

11. The probe card assembly of claim 5 , wherein the substrate comprises:

an embedded electrically conductive plane embedded in the substrate, and

a plurality of electrically conductive vias electrically connecting the guard conductors and the conductive plane.

12. The probe card assembly of claim 5 , wherein the signal conductors and the guard conductors comprise electrically conductive traces disposed on the substrate.

13. The probe card assembly of claim 5 , wherein the signal conductors and the guard conductors comprise electrically conductive wires bonded to the substrate.

14. The probe card assembly of claim 1 , wherein the signal conductor is disposed directly on an outer surface of the substrate.

15. The probe card assembly of claim 14 , wherein the pair of guard conductors is disposed directly on the outer surface of the substrate.

16. The probe card assembly of claim 15 , wherein the insulating material is disposed in part directly on the outer surface of the substrate between the pair of guard conductors.

17. The probe card assembly of claim 14 , wherein the insulating material is disposed in part directly on the outer surface of the substrate adjacent the signal conductor.

18. The probe card assembly of claim 1 , wherein at least part of the insulating material is disposed between the conductive material and the substrate.

19. The probe card assembly of claim 18 , wherein the signal conductor is disposed between at least part of the conductive material and the substrate.

20. The probe card assembly of claim 1 , wherein the signal conductor is disposed between at least part of the conductive material and the substrate.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Aug 7, 2025
From: HSBC BANK USA, NATIONAL ASSOCIATION
To: FORMFACTOR, INC.
Reel/Frame 072853/0001 →
SECURITY INTEREST IN UNITED STATES PATENTS AND TRADEMARKS Recorded Jul 12, 2016
From: FORMFACTOR, INC.; ASTRIA SEMICONDUCTOR HOLDINGS, INC.; CASCADE MICROTECH, INC.; MICRO-PROBE INCORPORATED
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 039184/0280 →