Capacitor in semiconductor device and method of manufacturing the same
View Patent ↗A capacitor may include at least one of a polysilicon layer over a semiconductor substrate; a capacitor dielectric layer over a polysilicon layer; an insulating layer over a capacitor dielectric layer; a metal layer connected to a capacitor dielectric layer through a first region of an insulating layer; an upper metal wiring layer connected to a metal layer over an insulating layer; and/or a lower metal wiring line layer connected to a polysilicon layer through a metal contact that passes through a second region of an insulating layer and a capacitor dielectric layer over the insulating layer.
1. A method of forming a capacitor comprising:
forming a polysilicon layer over a semiconductor substrate;
forming a capacitor dielectric layer over the polysilicon layer;
forming a metal layer over the capacitor dielectric layer;
forming an insulating layer over the capacitor dielectric layer;
forming a first contact hole in the insulating layer, wherein the metal is formed in the first contact hole; and
forming a second contact hole in the insulating layer and the capacitor dielectric layer,
wherein the second contact hole is in a different region than the first contact hole,
wherein the first contact hole and a portion of the second contact hole in the insulating layer are formed at substantially the same time,
wherein a portion of the second contact hole in the capacitor dielectric layer is formed after forming the second contact hole through the insulating layer,
wherein an etching mask is formed over the first contact hole before forming the portion of the second contact hole in the capacitor dielectric layer, and
wherein the etching mask is removed after forming the portion of the second contact hole in the capacitor dielectric layer.
2. The method of claim 1 , comprising forming a metal contact in the second contact hole.
3. The method of claim 1 , wherein the width of the first contact hole is larger than the width of the second contact hole.
4. The method of claim 1 , wherein:
the polysilicon layer is a lower capacitor electrode; and
the metal layer is an upper capacitor electrode.
5. The method of claim 1 , comprising implanting n-type impurity ions in the polysilicon layer.