Dual-bit memory device having trench isolation material disposed near bit line contact areas
View Patent ↗A dual-bit memory device is provided which includes trench isolation material disposed near bit line contact areas. For example, in one implementation a semiconductor memory device is provided in which each memory cell can store two bits of information. The memory device comprises a substrate, first and second buried bit lines in the substrate, a first bit line contact on the first buried bit line, a second bit line contact on the second buried bit line, and an insulator region disposed in the substrate between the first buried bit line and the second buried bit line. The insulator region prevents a current from flowing between the first buried bit line and the second buried bit line.
1. A semiconductor memory device, comprising:
a substrate;
a first buried bit line in the substrate;
a first bit line contact on the first buried bit line; and
a second buried bit line in the substrate;
a second bit line contact on the second buried bit line, wherein the second buried bit line is spaced apart from the first buried bit line; and
a plurality of insulator regions disposed in the substrate between the first buried bit line and the second buried bit line to prevent a current from flowing between the first buried bit line and the second buried bit line, wherein the plurality of insulator regions are substantially disposed between the first buried bit line and the second buried bit line only at the ends of the bit lines and between the first bit line contact and the second bit line contact, and wherein the plurality of insulator regions are disposed in the substrate only between buried bit lines.
2. A semiconductor memory device according to claim 1 , wherein the plurality of insulator regions comprises:
a plurality of trench isolation regions disposed in the substrate between the first buried bit line and the second buried bit line only at the ends of the bit lines and between the first bit line contact and the second bit line contact, wherein the plurality of trenches are filled with an insulator material to prevent a leakage current from flowing between the first buried bit line and the second buried bit line.
3. A semiconductor memory device according to claim 1 , further comprising:
a first insulator region disposed above the substrate over the first buried bit line, the first bit line contact extending through the first insulator region to the first buried bit line; and
a second insulator region disposed above the substrate over the second buried bit line, the second bit line contact extending through the second insulator region to the second buried bit line.
4. A semiconductor memory device according to claim 1 , further comprising:
an insulating spacer disposed over the substrate between the first buried bit line and the second buried bit line.
5. A semiconductor memory device according to claim 2 , wherein the plurality of trench isolation regions have a depth adequate to prevent a leakage current from flowing between the first buried bit line and the second buried bit line.
6. A semiconductor memory device according to claim 1 , wherein the semiconductor memory device comprises a short channel semiconductor memory device, and wherein the second buried bit line is spaced apart from the first buried bit line by a distance less than or equal to 1000 nanometers.
7. A semiconductor memory device according to claim 2 , wherein the plurality of trench isolation regions comprise an oxide.
8. A semiconductor memory device according to claim 2 , wherein the plurality of trench isolation regions extend into the substrate between 10 nanometers and 200 nanometers.
9. A semiconductor memory device according to claim 7 , wherein the plurality of trench isolation regions are formed using one of LOCalized Oxidation of Silicon (LOCOS) techniques and shallow trench isolation (STI) techniques.
10. A semiconductor memory device according to claim 6 , wherein the second buried bit line is spaced apart from the first buried bit line by a distance of approximately 30-1000 nanometers.