Methods for fabricating a split charge storage node semiconductor memory
View Patent ↗Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.
1. A method for fabricating a split charge storage node semiconductor memory device comprising the steps of:
forming a gate insulator layer on a surface of a semiconductor substrate;
depositing a layer of gate electrode forming material overlying the gate insulator layer and patterning the layer of gate electrode forming material to form a control gate electrode having a first edge and a second edge;
etching the gate insulator layer to form an undercut region at each of the first edge and the second edge of the control gate electrode, the undercut region exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode;
depositing a layer of silicon in the undercut region to form a first layer of silicon on the portion of the semiconductor substrate and a second layer of silicon on the underside portion of the control gate electrode;
oxidizing the layer of silicon to form a first layer of silicon oxide on the portion of the semiconductor substrate and a second layer of silicon oxide on the underside portion of the control gate electrode and leaving a void between the first layer of silicon oxide and the second layer of silicon oxide; and
filling the void with a charge storage material.
2. The method of claim 1 wherein the step of filling the void comprises the step of depositing a material selected from the group consisting of polycrystalline silicon, silicon nitride, and silicon rich silicon nitride.
3. The method of claim 1 wherein the step of forming a gate insulator comprises the step of growing a layer of silicon dioxide having a first physical thickness and a first effective oxide thickness.
4. The method of claim 3 wherein the steps of depositing a layer of silicon, oxidizing the layer of silicon, and filling the void with a charge storage material comprise the steps of forming an oxide-charge storage material-oxide structure having a physical thickness substantially equal to the first physical thickness.
5. The method of claim 4 wherein the steps of depositing a layer of silicon, oxidizing the layer of silicon, and filling the void with a charge storage material comprise the steps of forming an oxide-charge storage material-oxide structure having an effective oxide thickness less than the first effective oxide thickness.
6. The method of claim 1 further comprising the step of forming a first bit line and a second bit line in the semiconductor substrate, the first bit line aligned with the first edge and the second bit line aligned with the second edge.
7. The method of claim 1 wherein the step of depositing a layer of silicon comprises the step of depositing a layer of amorphous silicon.
8. A method for fabricating a split charge storage node semiconductor memory device comprising the steps of:
forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a surface of a semiconductor substrate;
depositing a layer of gate electrode forming material overlying the gate insulator layer and patterning the layer of gate electrode forming material to form a control gate electrode having a first edge and a second edge;
etching the gate insulator layer to form a first undercut region at the first edge and a second undercut region at the second edge, the first undercut region and the second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode;
forming a first charge storage node in the first undercut region and a second charge storage node in the second undercut region, each of the first charge storage node and the second charge storage node comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness, wherein the step of forming a first charge storage node and a second charge storage node comprises the steps of: depositing a layer of silicon in the first undercut region and the second undercut region, oxidizing the first layer of silicon, and depositing a layer of storage material on the oxidized first layer of silicon, wherein the layer of storage material comprises silicon nitride; and
etching the layer comprising silicon nitride to remove the layer from the first edge and the second edge.
9. The method of claim 8 further comprising the step of forming a first bit line aligned with the first edge and a second bit line aligned with the second edge.
10. The method of claim 9 further comprising the step of depositing and patterning a layer of conductive material to form a word line coupled to the control gate electrode.
11. A method for fabricating a split charge storage node semiconductor memory device comprising the steps of:
forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a surface of a semiconductor substrate;
depositing a layer of gate electrode forming material overlying the gate insulator layer and patterning the layer of gate electrode forming material to form a control gate electrode having a first edge and a second edge;
etching the gate insulator layer to form a first undercut region at the first edge and a second undercut region at the second edge, each of the undercut regions exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode;
depositing a first layer of oxide on the portion of the semiconductor substrate and on the underside portion in the first undercut region and in the second undercut region;
heating in an oxidizing ambient to densify the first oxide layer and to grow a thin second oxide layer on the portion of the semiconductor substrate and the underside portion, the steps of depositing a first oxide layer and heating in an oxidizing ambient leaving a void in each of the undercut regions; and
depositing a layer of charge storage material onto the densified first layer of oxide to fill the voids.
12. The method of claim 11 wherein the step of depositing a layer of charge storage material comprises the step of depositing a material selected from the group consisting of polycrystalline silicon, silicon nitride, and silicon rich silicon nitride.
13. The method of claim 12 wherein the steps of depositing a first oxide layer, heating in an oxidizing ambient, and depositing a layer of charge storage material comprise the step of forming a layered structure having an effective oxide thickness less than the first effective oxide thickness.
14. The method of claim 12 wherein the steps of depositing a first oxide layer, heating in an oxidizing ambient, and depositing a layer of charge storage material comprises the step of forming a layered structure having a second physical thickness substantially equal to the first physical thickness.
15. The method of claim 11 wherein the step of etching the gate insulator comprises the step of etching the gate insulator to form the first undercut region separated by a residual portion of the gate insulator layer from the second undercut region.
16. The method of claim 15 wherein the steps of depositing a first oxide layer, heating in an oxidizing ambient, and depositing a layer of charge storage material comprise the step of forming a first layered charge storage structure and a second layered charge storage structure separated by the residual portion of the gate insulator.
17. The method of claim 11 further comprising the step of depositing and patterning a layer of conductive material to form a word line coupled to the control gate electrode.