CMOS image sensor and method for manufacturing the same
View Patent ↗A CMOS image sensor and method for fabricating same are provided. The CMOS image sensor can include a gate electrode formed on an active area of a first conductive type semiconductor substrate, on which a photodiode area and a transistor area are defined; a low-density second conductive type diffusion region formed on the photodiode area at a first side of the gate electrode; a high-density second conductive the diffusion region formed on the transistor area at a second side of the gate electrode; an insulating layer formed on the semiconductor substrate at both sides of the gate electrode with a thickness less than a thickness of the gate electrode, but greater than a thickness of a gate insulating layer; and insulating layer sidewalls formed on the insulating layer at both sides of the gate electrode.
1. A method of fabricating a CMOS image sensor, comprising:
forming an insulating layer on a first conductive type semiconductor substrate;
defining a gate area by selectively removing the insulating layer such that a predetermined portion of a surface of the semiconductor substrate is exposed;
forming a gate insulating layer on the surface of the exposed semiconductor substrate;
forming a conductive layer on an entire surface of the semiconductor substrate and planarizing the conductive layer by adopting a top surface of the insulating layer as an end point, thereby forming a gate electrode on the gate insulating layer;
reducing a thickness of the insulating layer at both sides of the gate electrode;
forming an insulating layer sidewall on the insulating layer at both sides of the gate electrode;
forming a low-density second conductive type diffusion area on a photodiode area at a first side of the gate electrode; and
forming a high-density second conductive type diffusion area on a transistor area at a second side of the gate electrode.
2. The method according to claim 1 , wherein reducing the thickness of the insulating layer at both sides of the gate electrode comprises partially removing the insulating layer such that the insulating layer has a thickness of about 50% of a thickness of the gate electrode.
3. The method according to claim 1 , wherein forming the insulating layer sidewall comprises depositing an oxide on an entire surface of the substrate and performing an etching-back process.
4. The method according to claim 1 , wherein forming the gate insulating layer comprises performing a thermal oxidation process or a CVD process.
5. The method according to claim 1 , wherein forming the high-density second conductive type diffusion area comprises implanting a dose of 4×10 15 /cm −2 of As ions with ion implantation energy of about 80 keV.
6. The method according to claim 1 , wherein planarizing the conductive layer comprises performing a chemical mechanical polishing (CMP) process.