Method of fabricating a transistor
View Patent ↗A method of forming a transistor reduces leakage current and hot carrier effects, and therefore improves current performance. The method of forming a transistor includes selectively etching the semiconductor substrate to form a substrate protrusion and expose a buried source/drain implant region. A gate insulating layer covers the substrate protrusion and the first source/drain region. A gate conductor layer is selectively etched to form a gate pattern covering the sidewalls of the substrate protrusion and a portion of the semiconductor substrate adjacent to the sidewalls of the substrate protrusion. A second source/drain region is stacked over the top of the substrate protrusion. Contacts connected to the gate pattern and the first and second source/drain regions.
1. A method of forming a transistor comprising:
implanting ions into a semiconductor substrate to form a first source/drain region;
selectively etching the semiconductor substrate to form a substrate protrusion having a top and sidewalls;
forming a gate insulating layer covering the substrate protrusion and the first source/drain region;
depositing a gate conductor layer over the gate insulating layer;
selectively etching the gate conductor layer to form a gate pattern covering the sidewalls of the substrate protrusion and covering a portion of the semiconductor substrate adjacent to the sidewalls of the substrate protrusion;
forming a second source/drain region stacked over the top of the substrate protrusion using implanted ions; and
forming a contacts connected to the gate pattern and the first and second source/drain regions.
2. The method of claim 1 ,
wherein the first source/drain region is formed in the semiconductor substrate at a predetermined depth from the surface of the semiconductor substrate, and
wherein the substrate protrusion is etched to expose the first source/drain region.
3. The method of claim 1 , further comprising:
performing channel threshold voltage adjust implant on the substrate protrusion.
4. The method of claim 3 , wherein the channel threshold voltage adjust implant is performed using a tilt between 30 and 60° from a plane of a surface of the substrate.
5. The method of claim 3 , further comprising:
oxidizing surfaces of the substrate protrusion and the recessed semiconductor substrate to form a sacrificial oxide layer before the channel threshold voltage adjust implant; and
removing the sacrificial oxide layer after the channel threshold voltage adjust implant.
6. The method of claim 1 , wherein said forming the gate pattern comprises:
forming a mask over the gate conductor layer; and
dry etching the gate conductor layer exposed by the mask using the gate insulating layer as an etch stopper.
7. The method of claim 1 , wherein said gate pattern extends over a portion of the top of the substrate protrusion.
8. The method of claim 1 , wherein a channel region of the transistor is oriented vertically in the substrate protrusion.