Method of forming PIP capacitor
View Patent ↗A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor includes the steps of forming a lower electrode of a first polysilicon layer over a semiconductor substrate, forming a dielectric layer over the lower electrode, forming a second polysilicon layer over the dielectric layer, patterning the second polysilicon layer, implanting impurities into a side wall of the patterns of the second polysilicon layer and selectively etching the side wall of the patterns of the second polysilicon layer. The impurities are implanted to control an effective line width of the patterns of the second polysilicon layer as an upper electrode.
1. A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor, the method comprising:
forming a lower electrode using a first polysilicon layer over a semiconductor substrate;
forming a dielectric layer over the lower electrode;
forming a second polysilicon layer over the dielectric layer;
patterning the second polysilicon layer to form an upper electrode;
implanting impurities into a side wall of the patterned second polysilicon layer;
selectively etching said side wall having said impurities; and
forming a spacer over the sidewall of the patterned second polysilicon layer.
2. The method of claim 1 ,
wherein the first polysilicon layer is formed using a layer which is also used for a gate of a transistor, and
wherein the method further comprises the steps of:
forming a tungsten silicide layer over the first polysilicon layer; and
forming an additional polysilicon layer over the tungsten silicide layer.
3. The method of claim 2 ,
wherein the additional polysilicon layer is formed to be about half of the thickness of the second polysilicon layer.
4. The method of claim 3 , wherein the additional polysilicon layer functions as an anti-reflection coating layer.
5. The method of claim 1 , wherein the step of implanting the impurities is selectively performed using the same mask as the mask used for the step of patterning the second polysilicon layer.
6. The method of claim 1 , wherein said impurities are implanted at an angle with respect to a line perpendicular from a plane of an overall surface of said substrate.
7. The method of claim 1 , wherein said impurities are implanted to control an effective line width of the patterns of the second polysilicon layer forming the upper electrode.
8. The method of claim 7 , wherein the effective line width of the patterns of the second polysilicon layer forming the upper electrode is varied depending on an inclination angle at which the impurities are implanted.
9. The method according to claim 1 , wherein said forming a spacer over the sidewall of the patterned second polysilicon layer is done during a process of forming a spacer over the sidewall of a transistor.