Method of manufacturing CMOS image sensor
View Patent ↗Embodiments relate to a method of manufacturing a CMOS image sensor in which, when a buried photodiode is formed, a p-type impurity region may be formed simultaneously with a p-type LDD region in the photo diode region. Additionally, a p-type impurity region may be formed under side wall spacers, which may reduce leakage current of the photodiode. In embodiments, the method may include providing a semiconductor substrate divided into a pMOS region, a nMOS region, and a diode region, forming a shallow trench isolation (STI) on the semiconductor substrate, opening only the nMOS region and implanting low density n-type impurities to form an n-type LDD region, opening the diode region and pMOS region and implanting impurities to form a p-type impurity region and a p-type LDD region, opening only the diode region and implanting impurities to form an n-type impurity region, forming side wall spacers on both side walls of the gate, opening only the nMOS region and implanting high density n-type impurities to form an n-type source and drain region, and opening only the pMOS region and implanting high density p-type impurities to form p-type source and drain region.
1. A method, comprising:
providing a semiconductor substrate divided into a pMOS region, an nMOS region, and a diode region;
forming a shallow trench isolation (STI) in the semiconductor substrate;
forming at least one gate over the semiconductor substrate;
exposing only the nMOS region and implanting low density n-type impurities to form an n-type LDD region;
exposing the diode region and pMOS region and implanting impurities to form a p-type impurity region and a p-type LDD region; and
exposing only the diode region and implanting impurities to form an n-type impurity region.
2. The method of claim 1 , further comprising:
forming side wall spacers on side walls of the at least one gate;
exposing only the nMOS region and implanting high density n-type impurities to form an n-type source and drain region; and
exposing only the pMOS region and implanting high density p-type impurities to form a p-type source and drain region.
3. The method of claim 2 , wherein the sidewall spacers are formed after forming the p-type impurity region.
4. The method of claim 2 , wherein, in the step of ion implanting the n-type impurity to form the n-type source and drain region, the diode region is exposed and n-type impurities are simultaneously ion implanted.
5. The method of claim 1 , wherein the p-type impurity region and the p-type LDD region are simultaneously formed by a single impurity ion implantation when exposing the diode region and the pMOS region and implanting impurities to form the p-type impurity region and the p-type LDD region.
6. The method of claim 1 , wherein low density p-type impurity ions are implanted when the diode region and the pMOS region are exposed and the p-type impurity region and the p-type LDD region are formed.
7. The method of claim 1 , wherein n-type impurity ions are implanted at an angle of approximately 4 to 7 degrees when only the diode region is exposed and the n-type impurity region is formed.
8. The method of claim 7 , wherein a diode junction is formed on a bottom of the p-type impurity region under the at least one gate when the n-type impurities are implanted at the angle.
9. The method of claim 1 , wherein a buried B-photodiode is formed by exposing only the diode region and implanting impurities to form the n-type impurity region.
10. The method of claim 9 , wherein the n-type impurity region is formed to be deeper than the p-type impurity region.
11. The method of claim 1 , further comprising forming an R-photodiode and a G-photodiode in the diode region before forming the STI in the semiconductor substrate,
wherein a buried B-photodiode is formed by exposing only the diode region and implanting impurities to form the n-type impurity region.
12. The method of claim 11 , wherein the R-photodiode, G-photodiode, and the buried B-photodiode vertically overlap each other.
13. The method of claim 1 , further comprising forming a p-well region in the pMOS region before forming the gate on the semiconductor substrate.
14. The method of claim 1 , further comprising a gate oxide layer formed under the gate.
15. The method of claim 1 , wherein the n-type impurity region comprises arsenic (As).
16. The method of claim 1 , wherein the p-type impurity region comprises boron (B).
17. A method, comprising:
dividing a semiconductor substrate into a pMOS region, an nMOS region, and a diode region, the semiconductor substrate including at least one gate electrode;
forming a shallow trench isolation (STI) in the semiconductor substrate;
exposing only the nMOS region and implanting low density n-type impurities to form an n-type LDD region;
exposing the diode region and pMOS region and implanting impurities to simultaneously form a p-type impurity region and a p-type LDD region by a single implantation process;
exposing only the diode region and implanting impurities to form an n-type impurity region;
forming side wall spacers on side walls of the at least one gate electrode after forming the p-type impurity region;
exposing only the nMOS region and the diode region and simultaneously implanting high density n-type impurities to form an n-type source and drain region; and
exposing only the pMOS region and implanting high density p-type impurities to form p-type source and drain region.
18. The method of claim 17 , wherein the n-type impurity ions are implanted at an angle of approximately 4 to 7 degrees when only the diode region is exposed and the n-type impurity region is formed.