IP Library Granted Patent US 7,429,518
Granted Patent B2
US 7,429,518 · App. 11/617,209 · Granted Sep 30, 2008

Method for forming shallow trench isolation of semiconductor device

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Quick Facts
Patent No.
US 7,429,518
App. No.
11/617,209
Granted
Sep 30, 2008
Kind
B2
Abstract

A shallow trench isolation well is formed to be very thin in a highly integrated semiconductor device. When critical dimension (CD) is small, it is difficult to reduce the width of the photosensitive layer pattern for forming a trench to no more than a predetermined value due to limitations on the photolithography process.

Claims (20)

1. A method comprising:

forming a photosensitive layer pattern over a semiconductor;

forming a copper layer over the substrate where the photosensitive layer pattern is formed;

planarizing the copper layer using a CMP process until a surface of the photosensitive layer pattern is exposed;

removing the photosensitive layer pattern; and

etching the substrate using the copper layer as a mask to form a trench.

2. The method of claim 1 , wherein the removal of the photosensitive layer pattern is performed by a wet etching process.

3. The method of claim 2 , wherein the wet etching process is performed using one of an SC- 1 and an SC- 2 cleansing solution.

4. The method of claim 1 , further including removing the copper layer on the substrate.

5. A method of forming an isolation trench of a semiconductor device comprising:

forming a photosensitive layer pattern over a semiconductor substrate using a photolithography process;

forming a copper layer over the substrate where the photosensitive layer pattern is formed;

planarizing the copper layer using a CMP process until a surface of the photosensitive layer pattern is exposed;

removing the photosensitive layer pattern through a wet etching process;

etching the substrate using the copper layer as a mask to form a trench;

removing the copper layer on the substrate;

forming a trench oxide layer over the substrate where the trench is formed; and

planarizing the trench oxide layer using the CMP process.

6. The method of claim 5 , wherein the copper layer is formed using an electro-chemical plating (ECP) method.

7. The method of claim 5 , wherein the wet etching process is performed using SC- 1 or SC- 2 cleansing solution.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041427/0106 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →