IP Library › Granted Patent US 7,684,254
Granted Patent B2
US 7,684,254 · App. 11/617,670 · Granted Mar 23, 2010

Flash memory device and method of erasing memory cell block in the same

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 7,684,254
App. No.
11/617,670
Granted
Mar 23, 2010
Kind
B2
Abstract

A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block to be erased among the plurality of blocks to be erased. A controlling logic circuit is configured to output an erase command signal and an erase block address corresponding to one of the blocks to be erased. A block address comparing section is configured to compare the erase block address output by the controlling logic circuit with the last block address, and output an erase progress signal based on the comparison of the erase block address and the last block address to the controlling logic circuit. The controlling logic circuit outputs an erase block address of to another block to be erased until the erase progress signal indicates that the last block to be erased has been or is being erased.

Claims (21)

1. A method of erasing blocks in a flash memory device, the method comprising:

storing a start block address corresponding to an address of the first block to be erased among a plurality of blocks to be erased;

inputting a dummy confirm command for adjusting input timing of a last block address, the last block address corresponding to an address of the last block to be erased among the plurality of blocks to be erased;

storing the last block address after inputting the dummy confirm command;

performing an erase operation starting with the first block until the last block is erased;

determining whether or not a block that is being erased or has been erased most recently corresponds to the last block to be erased among the plurality of blocks; and

ending the erase operation according to the determining step.

2. The method of claim 1 , further comprising:

inputting an erase setup command for the erasing operation before storing the start block address.

3. The method of claim 1 , further comprising:

inputting an erase confirm command before the erasing operation.

4. The method of claim 1 , wherein the step of the performing the erasing operation includes:

erasing the block selected by the start block address; and

increasing the start block address to select the next block to be erased,

wherein the start block address is increased up to the last block address so that every block in the plurality of blocks to be erased is erased.

5. The method of claim 4 , further comprising:

determining whether or not the erasing operation has been properly performed after performing the erasing operation.

6. The method of claim 1 , wherein the step of the performing the erasing operation includes:

erasing the block selected by the start block address; and

selecting another block address from the plurality of blocks to be erased,

wherein the erasing and selecting steps are repeated until the last block has been erased.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2007
From: JUNG, MIN JOONG; JEONG, BYOUNG KWAN; KANG, TAI KYU
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 018827/0984 →
Priority Claims (1)
KR 10-2006-0096184 · Sep 29, 2006 · national
Continuity (1)
Related Publication 20080084766A1 · Apr 10, 2008