Method of fabrication of phase-change memory
A phase-change memory and fabrication method thereof. The phase-change memory comprises a transistor, and a phase-change material layer. In particular, the phase-change material layer is directly in contact with one electrical terminal of the transistor. Particularly, the transistor can be a field effect transistor or a bipolar junction transistor.
1. A method of fabricating a phase-change memory element, comprising: forming a patterned hardmask layer with a first width on a phase-change material layer; etching the phase-change material layer using the patterned hardmask layer with first width as mask; trimming the patterned hardmask layer until a second width of the patterned hardmask layer is achieved, obtaining a tapered profile hardmask layer/phase-change material layer stack with a bottom phase-change material pedestal; and etching the tapered profile hardmask layer/phase-change material layer stack using the patterned hardmask layer with the second width as mask, obtaining a straight profile hardmask layer/phase-change material layer stack with the bottom phase-change material pedestal.
2. The method as claimed in claim 1 , before forming a patterned hardmask layer, further comprising:
providing a dielectric layer with a trench passing therethrough on a substrate; and
forming the phase-change material layer on the dielectric layer that completely fills the trench.
3. The method as claimed in claim 2 , wherein the patterned hardmask layer is perpendicular to the trench.
4. The method as claimed in claim 2 , wherein the height of the phase-change material layer disposed in the trench is larger than depth of the trench.
5. The method as claimed in claim 1 , wherein the patterned hardmask layer is trimmed by dry trimming process or solution trimming process.
6. The method as claimed in claim 2 , wherein the trench has a depth between 20˜150 nm.
7. The method as claimed in claim 1 , wherein the bottom phase-change material pedestal has the first width.
8. A method of fabricating a phase-change memory element, comprising:
providing a substrate with a transistor;
forming a dielectric layer on the substrate;
forming a trench passing through the dielectric layer to expose one terminal of the transistor;
forming a phase-change material layer on the dielectric layer that completely fills the trench;
forming a conductive layer on the phase-change material layer;
forming a patterned hardmask layer with first width on the conductive layer, wherein the patterned hardmask layer is perpendicular to the trench;
etching the phase-change material layer and the conductive layer using the patterned hardmask layer with first width as mask;
trimming the patterned hardmask layer until a second width of the patterned hardmask layer is achieved, obtaining a tapered profile hardmask layer/conductive layer/phase-change material layer stack with a bottom phase-change material pedestal; and
etching the tapered profile hardmask layer/conductive layer/phase-change material layer stack using the patterned hardmask layer with the second width as mask, obtaining a straight profile hardmask layer/conductive layer/phase-change material layer stack with the bottom phase-change material pedestal.
9. The method as claimed in claim 8 , in the step of etching the tapered profile hardmask layer/conductive layer/phase-change material layer stack using the patterned hardmask layer as mask, wherein the remaining conductive layer serves as a bit line.
10. The method as claimed in claim 8 in the step of forming a phase-change material layer on the dielectric layer and completely fill the trench, wherein the height of the phase-change material layer disposed in the trench is larger than depth of the trench.
11. The method as claimed in claim 8 further comprising:
where the dielectric layer is covered by a protective layer prior to forming the trench.
12. The method as claimed in claim 8 , wherein the patterned hardmask layer is trimmed by dry trimming process or solution trimming process.
13. The method as claimed in claim 8 , wherein the trench has a depth between 20˜150 nm.
14. The method as claimed in claim 8 , wherein the trench is parallel to a line comprising a gate or base electrode.
15. The method as claimed in claim 8 , wherein only the conductive layer is completely etched to second width defined by patterned hardmask.
16. The method as claimed in claim 8 , wherein the bottom phase-change material pedestal has the first width.