Flexible and area efficient column redundancy for non-volatile memories
View Patent ↗A non-volatile memory wherein bad columns in the array of memory cells can be removed is described. Additionally, substitute redundant columns can replace the removed columns. Both of these processes are performed on the memory in a manner that is externally transparent and, consequently, need not be managed externally by the host or controller to which the memory is attached. An inventory of the bad columns can be maintained on the memory. At power up, the list of bad columns is used to fuse out the bad columns. The memory may also contain a number of redundant columns that can be used to replace the bad columns.
1. A method of operating an integrated circuit comprising:
providing a plurality of memory cells arranged into a plurality of columns;
providing a plurality of latches to hold data associated with a corresponding one of said columns;
providing a shift register having a plurality of stages with an output coupled to an enable input of a corresponding latch;
determining that one or more of said columns each includes a defective memory cell;
fusing out the shift register stages corresponding to the columns determined to include a defective memory cell;
loading a strobe bit into a first stage of the shift register to enable coupling of the corresponding first latch to an input line; and
clocking the shift register to advance the strobe bit from the first stage of the shift register to the subsequent stages to enable coupling of the corresponding subsequent latches to the input line, wherein when a stage is fused out the strobe bit is advanced through the fused out stage without being clocked and without the fused out stage enabling the corresponding latch to an input line.
2. The method of claim 1 , wherein the memory cells are multi-state memory cells.
3. The method of claim 1 , further comprising:
reading a memory portion on the integrated circuit containing information on the columns including a defective memory cell, wherein said fusing out one or more of the shift registers is based on the contents of said memory portion.
4. The method of claim 3 , wherein said fusing out is performed at power up.
5. The method of claim 3 , wherein said information on the columns including a defective memory cell is stored in more than one memory location.
6. The method of claim 1 , further comprising:
asserting a control signal to the shift register when the strobe bit reaches the last stage of the shift register, wherein in response to the control signal the shift register advances the strobe bit from the last stage of the shift register to the preceding stages.
7. The method of claim 1 , wherein said determining that one or more of said columns each includes a defective memory cell is performed as part of a test process.
8. The method of claim 1 , further comprising:
subsequently determining that one or more additional columns each includes a defective memory cell.