Bit error detector for iterative ECC decoder
View Patent ↗An iterative decoder includes at respective variable nodes, that is, at nodes that correspond to the bits of the code word, bit error detectors that after convergence determine if the respective hard decision bit values have changed from the bit values provided by the channel. The change in value for a given bit indicates that a bit error has been corrected. The bit error detector, for message-passing decoders that perform calculations by addition rather than multiplication, can be readily implemented as an XOR gate. Thus, a bit error is detected at the variable node by XOR'ing the sign bits of the input symbol and the variable node sum. After convergence, the output values produced by the bit error detectors at the respective variable nodes are added together using an adder tree that accumulates the detected bit errors for an entire date block, or ECC code word. Alternatively, the system may group the bits into respective code word symbols and combine the bit error values into symbols-with-errors values using, for example, XOR sub-trees that produce, for each symbol, a single error value. The error value for a given symbol indicates that the symbol is either error-free or includes one or more bit errors, and a total count of the symbols with errors is produced by adding the error values together.
1. A bit error detector for use with an iterative decoder, the bit error detector including:
one or more input lines for receiving at least a sign bit of an input symbol and a sign bit of a corresponding variable node sum;
means for determining if the sign bit of the variable node sum and the sign bit of the input symbol are the same; and
an output line that provides an error value signal if the sign bits differ.
2. The bit error detector of claim 1 wherein the means for determining is an exclusive-OR gate.
3. The bit error detector of claim 1 wherein the means for determining is an adder.
4. The bit-error detector of claim 1 wherein the means for determining is a comparitor.
5. An iterative decoder for decoding a plurality of bits, the decoder including
a plurality of check nodes;
a plurality of variable nodes that produce respective updated sign values that correspond to input symbols; and
a plurality of bit error detectors that produce error values for the respective bits, the bit error detectors detecting bit errors for the respective bits for which the updated sign values differ from sign bits of the corresponding input symbols.
6. The iterative decoder of claim 5 wherein the bit error detectors are exclusive OR gates.
7. The iterative decoder of claim 5 wherein the input symbols are provided by a detector and consist of a sign bit and associated confidence information, and the variable nodes produce sums that include the updated sign values and associated confidence values.
8. The iterative decoder of claim 7 wherein the variable nodes provide the confidence information from the respective sums to the check nodes for a next iteration.
9. The iterative decoder of claim 5 further including an adder tree that produces a total bit count by adding together the bit error values produced by the bit error detectors.
10. The iterative decoder of claim 5 further including an accumulator that produces a total bit error count based on the bit error values produced by the bit error detectors.
11. A method for detecting bit errors in iterative decoding, the method including the steps of:
A. processing respective input symbols that consist of at least sign bits to produce sums that consist of at least updated sign bits;
B. producing bit error values if the sign bits of respective input symbols and the sign bits of the corresponding sums are different and counting the values to produce a count; and
C. determining if convergence has occurred and if so using the count produced in step B as error count;
D. if convergence has not occurred updating the sum and repeating steps B-D until either convergence or a stop condition occurs.
12. The method of claim 11 further including in the step of updating the sum
processing the updated sign bits and associated confidence information in accordance with code constraints to produce associated messages, and
further processing the input symbols and the associated messages to produce next updated sign bits and associated confidence information.
13. The method of claim 11 wherein the step of producing bit error values includes comparing the sign bits of respective input symbols and the corresponding sums.
14. The method of claim 11 wherein the step of producing bit error values includes exclusive OR'ing the sign bits of respective input symbols and the corresponding sums.
15. The method of claim 11 wherein the step of producing bit error values includes adding the sign bits of the respective input symbols and the corresponding sums.
16. The method of claim 11 further including the steps of
determining if the error count exceeds a predetermined threshold, and
if so, re-vectoring the data to another storage location.
17. The method of claim 11 wherein the step of counting includes adding together the bit error values.
18. The method of claim 16 wherein the step of counting the bit errors includes using an accumulator.
19. The method of claim 11 further including
grouping the bits into n-bit symbols,
producing error values for the respective symbols that include detected bit errors, and
counting the error values to produce the error count.
20. The method of claim 19 further including the steps of
determining if the count exceeds a predetermined threshold,
if so, re-vectoring the data to another storage location.