Current compliant sensing architecture for multilevel phase change memory
View Patent ↗A memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change element in the presence of a read current. The memory circuit includes a sense amplifier that defines a sensing node. Circuitry selectively places the bit line in data communication with the sensing node, defining a selected bit line. A current source produces a read current, and a switch selectively applies the read current to the sensing node. Logic is in electrical communication with the sensing node to control the total energy to which the phase change material is subjected in the presence of the read current so that the data state remains consistent.
1. A memory device, comprising:
a memory cell coupled to a bit line and a word line and including phase change material having a data state associated therewith;
a sense amplifier defining a sensing node;
circuitry to selectively place the bit line in signal communication with the sensing node, defining a selected bit line;
a current source to produce a read current;
a switch coupled to selectively apply the read current to the sensing node; and
circuitry coupled to the switch and responsive to a signal from the selected bit line to control a quantity of energy to which the phase change material in the memory cell associated with the selected bit line is subjected to in the presence of the read current so that the data state remains consistent, wherein the sense amplifier includes a reference input, and circuitry to supply a reference voltage having a plurality of values to the reference input, and the sense amplifier is adapted to sense a voltage on the sensing node relative to said plurality of values in a sensing sequence to detect multiple bits of data from a selected memory cell.
2. The memory device of claim 1 , wherein the circuitry includes a detector coupled to the sensing node, to detect a voltage on the sensing node, and the logic to cause the switch to terminate electrical communication of the current source with the sensing node.
3. The memory device of claim 1 , wherein the circuitry includes logic responsive to a read enable signal indicating a start of a read cycle to control the switch to selectively place the current source in electrical communication with the sensing node, with the logic being responsive to an output from the sense amplifier to cause the switch to terminate electrical communication of the current source with the sensing node.
4. The memory device of claim 1 , wherein the circuitry includes a detector coupled to the sensing node, to detect a voltage on the sensing node, and logic responsive to a read enable signal indicating a start of a read cycle to control the switch to selectively place the current source in electrical communication with the sensing node, with the logic being responsive to an output from the detector to cause the switch to terminate electrical communication of the current source with the sensing node.
5. The memory device of claim 1 , wherein the current source comprises a current mirror.
6. The memory device of claim 1 , wherein the current source includes a field effect transistor biased to operate as a constant current device.
7. The memory device of claim 1 , wherein the memory cell is characterized by having a relatively high resistance data state, at least one relatively intermediate resistance data state, and a relatively low resistance data state, and wherein the circuitry controls the switch to terminate electrical communication of the current source with the sensing node, in response to detection of a voltage on the sensing node that is high enough to ensure proper sensing of the relatively high resistance data state.
8. The memory device of claim 1 , wherein the memory cell is characterized by having a relatively high resistance data state, at least one relatively intermediate resistance data state, and a relatively low resistance data state, and wherein the circuitry controls the switch to terminate electrical communication of the current source with the sensing node, in response to detection of a voltage on the sensing node that is high enough to ensure proper sensing of the data state of the memory cell.
9. A memory device, comprising:
a memory cell coupled to a bit line and a word line and including phase change material having a data state associated therewith;
a plurality of sense amplifiers coupled in parallel to a sensing node, said plurality of sense amplifiers including respective reference inputs, and including circuitry to supply reference voltages to the respective reference inputs having a plurality of values, and so that the plurality of the sense amplifiers detect multiple bits of data from a selected memory cell;
circuitry to selectively place the bit line in signal communication with the sensing node, defining a selected bit line;
a current source to produce a read current;
a switch coupled to selectively apply the read current to the sensing node; and
circuitry coupled to the switch and responsive to a signal from the selected bit line to control a quantity of energy to which the phase change material in the memory cell associated with the selected bit line is subjected to in the presence of the read current so that the data state remains consistent.
10. A memory device, comprising:
a memory cell coupled to a bit line and a word line and including phase change material having a data state associated therewith;
a sense amplifier defining a sensing node;
circuitry to selectively place the bit line in signal communication with the sensing node, defining a selected bit line;
a current source to produce a read current;
a switch coupled to selectively apply the read current to the sensing node; and
circuitry coupled to the switch and responsive to a signal from the selected bit line to control a quantity of energy to which the phase change material in the memory cell associated with the selected bit line is subjected to in the presence of the read current so that the data state remains consistent, wherein the circuitry includes a detector coupled to the sensing node, to detect a voltage on the sensing node, and the logic to cause the switch to terminate electrical communication of the current source with the sensing node.
11. A method of reading a memory cell including phase change material having a data state associated therewith, said method comprising:
applying a read current to said memory cell to read said data state;
sensing a voltage on a sensing node relative to a plurality of reference voltages in a sensing sequence to detect multiple bits of data from a selected memory cell; and
controlling the total energy to which the phase change material is subjected in the presence of said read current so that data associated with the phase change material remains consistent.
12. The method of claim 11 , wherein controlling further includes regulating a magnitude of said read current to be within predetermined levels for a predetermined duration of time.
13. The method of claim 11 , wherein controlling further includes regulating the read current to prevent crystallizing a volume of the phase change material to an extent that defines a change in data states associated therewith.
14. The method of claim 11 , wherein controlling further includes regulating a magnitude and pulse width of the read current to prevent crystallizing a volume of the phase change material to an extent that defines a change in data states associated therewith.
15. The method of claim 11 , and wherein said applying includes connecting a current source to the sensing node, and said controlling includes detecting a voltage on the sensing node, and in response to the detecting, disconnecting the current source from the sensing node.
16. The method of claim 11 , including controlling the magnitude of the read current, so that the read current remains substantially constant during reading of the memory cell.
17. The method of claim 11 , wherein the memory cell is characterized by having a relatively high resistance data state, at least one relatively intermediate resistance data state, and a relatively low resistance data state, and wherein said applying includes connecting a current source to the sensing node, and said controlling includes detecting a voltage on the sensing node, and in response to the detecting, disconnecting the current source from the sensing node, wherein said detected voltage on the sensing node is high enough to ensure proper sensing of the relatively high resistance data state.
18. The method of claim 11 , wherein the memory cell is characterized by having a relatively high resistance data state, at least one relatively intermediate resistance data state, and a relatively low resistance data state, and wherein said applying includes connecting a current source to the sensing node, and said controlling includes detecting a voltage on the sensing node, and in response to the detecting, disconnecting the current source from the sensing node, wherein said detected voltage on the sensing node is high enough to ensure proper sensing of the data state of the memory cell.
19. A memory device, comprising:
a memory cell coupled to a bit line and a word line and including phase change material having a data state associated therewith;
a sense amplifier defining a sensing node;
circuitry to selectively place the bit line in signal communication with the sensing node, defining a selected bit line;
a current source to produce a read current;
a switch coupled to selectively apply the read current to the sensing node; and
circuitry coupled to the switch and responsive to a signal from the selected bit line to control a quantity of energy to which the phase change material in the memory cell associated with the selected bit line is subjected to in the presence of the read current so that the data state remains consistent, the circuitry including logic responsive to a read enable signal indicating a start of a read cycle to control the switch to selectively place the current source in electrical communication with the sensing node, with the logic being responsive to an output from the sense amplifier to cause the switch to terminate electrical communication of the current source with the sensing node.
20. A method of reading a memory cell including phase change material having a data state associated therewith, said method comprising:
applying a read current to said memory cell to read said data state including coupling the memory cell to a sensing node and connecting a current source to the sensing node; and
controlling the total energy to which the phase change material is subjected in the presence of said read current so that data associated with the phase change material remains consistent, said controlling including detecting a voltage on the sensing node, and in response to the detecting, disconnecting the current source from the sensing node.