Chemical mechanical polishing test structures and methods for inspecting the same
Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
1. A semiconductor die comprising a plurality of dummy structures positioned and sized to minimize defects during chemical mechanical polishing, at least one of the dummy fillings being coupled to an underlying test structure so as to together form a voltage contrast test structure and wherein at least one of the dummy filling does not form part of a voltage contrast test structure.
2. A semiconductor die as recited in claim 1 , the semiconductor die further comprising:
a plurality of conductive layers; and
a substrate,
wherein the underlying test structure comprises a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling.
3. A semiconductor die as recited in claim 2 , the underlying test structure further comprising a via coupling the first layer portion to the substrate.
4. A semiconductor die as recited in claim 3 , wherein the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
5. A semiconductor die as recited in claim 3 , wherein the via is a redundant via.
6. A semiconductor die as recited in claim 3 , wherein at least one of the vias coupled between the plurality of layers and between the underlying test structure and the first layer portion is a redundant via.
7. A semiconductor die as recited in claim 1 , wherein a plurality of adjacent dummy filling are coupled to a plurality of adjacent underlying test structures to form a plurality of adjacent voltage contrast test structures, the semiconductor die further comprising a plurality of conductive layers and a substrate, wherein the adjacent underlying test structures comprise a plurality of adjacent layer portions formed from the plurality of conductive layers that are each coupled through at least one via to at least one of the dummy fillings, wherein at least one of the adjacent layer portions is coupled to the substrate and at least one of the adjacent layer portions is not coupled to the substrate.
8. A semiconductor die as recited in claim 7 , wherein a plurality of adjacent layer portions are coupled to the substrate and another plurality of the adjacent layer portions are not coupled to the substrate, wherein each of the adjacent layer portions that is coupled to the substrate is adjacent to another adjacent layer portion that is not coupled to the substrate.
9. A semiconductor die as recited in claim 1 , wherein a plurality of adjacent dummy filling are coupled to a plurality of adjacent underlying test structures to form a plurality of adjacent voltage contrast test structures, the semiconductor die further comprising a substrate, wherein at least one of the dummy fillings is coupled to the substrate and at least one of the dummy fillings is not coupled to the substrate.
10. A semiconductor die as recited in claim 9 , wherein a plurality of the adjacent dummy fillings are coupled to the substrate and another plurality of the adjacent dummy fillings are not coupled to the substrate, wherein each of the adjacent dummy fillings that is coupled to the substrate is adjacent to another of the adjacent dummy filling that is not coupled to the substrate.