Active matrix display device and semiconductor device for timing control thereof
An active matrix display device includes: a plurality of pixels that are disposed in a matrix; a plurality of image signal lines that are disposed to correspond to respective columns of the pixels; a plurality of scanning signal lines that are disposed to correspond to respective rows of the pixels; an image signal line driving unit that supplies image signals for driving the pixels to the image signal lines; and a timing control circuit that transmits an image display control signal to the image signal line driving unit with a predetermined cycle even during a vertical blanking period. The timing control circuit performs a control operation allows the image signal line driving unit to intermit a read operation of image display data during the first period that is defined within the vertical blanking period and that includes at least a second half of the vertical blanking period.
1. An active matrix display device comprising:
a plurality of pixels that are disposed in a matrix including a plurality of columns and rows;
a plurality of image signal lines that are disposed to correspond to respective columns of the pixels;
a plurality of scanning signal lines that are disposed to correspond to respective rows of the pixels;
an image signal line driving unit that supplies image signals for driving the pixels to the image signal lines; and
a timing control circuit that transmits an image display control signal to the image signal line driving unit with a predetermined cycle even during a vertical blanking period,
wherein the timing control circuit performs a control operation that allows the image signal line driving unit to intermit a read operation of image display data during a first period, the first period being defined within the vertical blanking period and including at least an entire second half of the vertical blanking period.
2. The active matrix display device according to claim 1 ,
wherein the timing control circuit erases a horizontal start pulse to the image signal line driving unit during the first period.
3. The active matrix display device according to claim 1 ,
wherein the timing control circuit sets a first time point and a second time point, the first time point is set at a predetermined time point within a time period where the read operation of the image display data is intermitted, and the second time point is set at a time point that the read operation of image display data is started in a first horizontal display period after the vertical blanking period is completed, and
wherein the timing control circuit performs a control operation to allow the image signal line driving unit to intermit an updating operation of an output voltage during a period between the first time point and the second time point.
4. The active matrix display device according to claim 3 ,
wherein the timing control circuit erases a latch pulse to the image signal line driving unit during the first time point and the second time point.
5. The active matrix display device according to claim 3 ,
wherein the timing control circuit sets the first time point and the second time point so that a time period between the first time point and the second time point is shorter than one horizontal scanning period of the vertical scanning period.
6. The active matrix display device according to claim 3 ,
wherein the timing control circuit sets the first time point and the second time point so that a time period between the first time point and the second time point includes an input inhibiting period of a latch pulse that is determined in advance in accordance with a structure of the image signal line driving unit.
7. The active matrix display device according to claim 1 ,
wherein the timing control circuit sets the length of the first period exceeds half the length of the vertical blanking period.
8. A semiconductor device for timing control of an active matrix display device that includes a plurality of pixels that are disposed in a matrix including a plurality of columns and rows, a plurality of image signal lines that are disposed to correspond to respective columns of the pixels, a plurality of scanning signal lines that are disposed to correspond to respective rows of the pixels, and an image signal line driving unit that supplies image signals for driving the pixels to the image signal lines, the semiconductor device comprising:
a timing control circuit that transmits an image display control signal to the image signal line driving unit with a predetermined cycle even during a vertical blanking period,
wherein the timing control circuit performs a control operation that allows the image signal line driving unit to intermit a read operation of image display data during a first period, the first period being defined within the vertical blanking period and including at least an entire second half of the vertical blanking period.