Fully associative banking for memory
View Patent ↗A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.
1. A memory system that facilitates read access in a memory device comprising:
a plurality of row address buffers, each row address buffer being configured to store and be associated with high order addresses, wherein the high order addresses include one or more most significant bits of memory addresses; and
a plurality of row data buffers, each row data buffer configured to store non-transitory data of a memory array of a plurality of memory arrays,
wherein each row address buffer freely associates with any row data buffer in the plurality of row data buffers such that a row data buffer paired to a row address buffer stores a portion of data of the memory array corresponding to a complete memory address;
wherein the complete memory address has a high order address stored in the row address buffer and a lower order address which, when combined with the high order address, addresses the portion of data of the memory array, and each row address buffer is freely associated with one or more row data buffers, separately and one at a time, in response to incoming memory access requests; and
a controller that associates each row address buffer with a software thread sending respective high order addresses such that each row address buffer of the plurality of row address buffers is not reloaded when at least one other software thread sends at least one other row address,
the memory array is a flash memory array and the memory device is a non-volatile memory device, wherein the controller freely associates each row address buffer with any row data buffer of the plurality of row data buffers with a portion of bits from the complete memory address,
the lower address selects the row data buffer from the plurality of row data buffers, wherein the controller freely associates each row address buffer with any row data buffer of the plurality of row data buffers with a multiplexor, wherein the multiplexor receives the portion of bits from the controller to select the memory array from the plurality of memory arrays to load the portion of data of the memory array corresponding to the complete memory address into the row data buffer selected, and
the high order address corresponds to a locality region of the software thread, wherein the multiplexor receives the portion of data of the memory array corresponding to the complete memory address from each of the plurality of memory arrays and selects data from one of the memory arrays to load into the row data buffer based on the portion of bits.
2. The system of claim 1 , the software thread is associated with the row address buffer storing the high order address to facilitate future read accesses.
3. The system of claim 1 , wherein the software thread receives the portion of data of the memory array from the row data buffer instead of from the memory array.
4. The system of claim 3 , the controller utilizes a replacement policy to free buffers from the plurality of row address buffers and the plurality of row data buffers, wherein the controller associates the software thread with more than one row data buffer and maintains subsequent memory accesses to the row data buffer despite context switching.
5. The system of claim 4 , the replacement policy is a least recently used policy.
6. The system of claim 1 , a number of row address buffers equals a number of row data buffers.