Stalling processor pipeline for synchronization with coprocessor reconfigured to accommodate higher frequency operation resulting in additional number of pipeline stages
View Patent ↗A processor system that includes a main processor, and a coprocessor connected to the main processor. If the number of instruction execution cycles of an extended instruction executed by the coprocessor is larger than the number of instruction execution cycles of a basic instruction executed by the main processor, a pipeline process for a subsequent instruction retrieved after the extended instruction is stopped at least for a period corresponding to a difference between the number of instruction execution cycles of the extended instruction and the number of instruction execution cycles of the basic instruction.
1. A processor system comprising:
a main processor having an instruction fetch unit fetching an instruction to be executed from an instruction memory,
an instruction decode unit decoding an instruction to be executed; and
an instruction execution unit executing an basic instruction to be executed in said main processor side, said main processor performing a pipeline processing by using said instruction fetch unit, said instruction decode unit, and said instruction execution unit; and
a coprocessor coupled to said main processor and having another instruction execution unit executing an extended instruction to be executed in said coprocessor side, the number of stages of said another instruction execution unit being larger than the number of stages of said execution unit in said main processor when an frequency flag indicates that a high speed clock signal is provided to said processor system,
wherein said main processor ceases said pipe line processing for a preliminarily determined period without responding to a wait signal from said coprocessor, when said frequency flag indicates that a high speed clock signal is provided to said processor system and said instruction decode unit decodes said extended instruction.
2. The processor system according to claim 1 , wherein said main processor ceases said pipe line processing by stopping an operation of said instruction fetch unit and an operation of said instruction decode unit.
3. The processor system according to claim 1 , wherein the number of stages of said another instruction execution unit is equal to said number of stages of said instruction execution unit when said frequency flag indicates that a low speed clock signal is provided to said processor system.
4. The processor system according to claim 1 , wherein said coprocessor further has another instruction decode unit decoding said extended instruction and said another instruction decode unit outputs a control signal for executing said extended instruction.
5. The processor system according to claim 4 , wherein each of said instruction decode unit and said another instruction decode unit refers to said frequency flag indicating whether a high speed clock signal is provided to said processor or not.
6. The processor system according to claim 1 , wherein the instruction decode unit decodes the instruction retrieved by the instruction fetch unit.