Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
View Patent ↗A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
1. A vertical oriented EEPROM memory array, comprising:
a) a column of two-transistor memory cells arranged into a plurality of rows of byte-wide segments, wherein each byte-wide segment is separately addressable,
b) a byte-word line decoder located at an end of said column connecting to a word line of said byte-wide segments,
c) an array of said two-transistor memory cells arranged in a plurality of columns of byte wide segments, wherein each column contains said byte-word line decoder.
2. The memory array of claim 1 , further comprising:
a) a first plurality of metal lines connecting bit lines and a source line to said memory cells in each said byte-wide segment contained within each column of said plurality of columns and an output of said byte-word line decoder to said word line of a first byte-wide segment,
b) a second plurality of metal lines connecting between said byte-word line decoder and said word line of each additional byte-wide segment beyond said first byte-wide segment that are contained within each column of said plurality of columns.
3. The memory array of claim 2 , wherein said first plurality of metal lines are routed along a length and distributed across a width of each said column in a first layer of metal lines.
4. The memory array of claim 3 , wherein said first plurality of metal lines connect to eight bit lines, one source line and one word line.
5. The memory array of claim 2 , wherein said second plurality of metal lines are routed along a length and distributed across the width of each said column in a plurality of wiring layers of metal lines located above a first layer of metal lines.
6. The memory array of claim 5 , wherein said second plurality of metal lines connect separately to byte segments in a column and are routed in groups of ten metal lines on each wiring layer above said first wiring layer.
7. The memory array of claim 5 , wherein said second plurality of metal lines are clustered together with a plurality of global word lines at the side of said column of byte-wide segments when a number of wiring layers is limited.
8. A byte-word line decoder, comprising:
a) a decoding means for selecting a byte-word of data stored in an EEPROM memory array,
b) an interconnection means for connecting said decoding means to a plurality of byte-word lines in said memory array,
c) a wiring means for placing said interconnection means onto a plurality of metalization layers above a bit line metalization layer.
9. The decoder of claim 8 , wherein said wiring means places byte-word lines within said plurality of metalization layers located above a column of byte-word bit lines on said bit line metalization layer and running in parallel with said byte-word bit lines.
10. The decoder means of claim 8 , wherein said wiring means places byte-word lines within said plurality of metalization layers located above a plurality of columns of byte-word bit lines on said bit line metalization layer and running orthogonal to said byte-word bit lines.