Patent Assignment
Reel/Frame 037513/0535
Merger
Recorded: 2016-01-13
Pages: 37
Assignor
ABEDNEJA ASSETS AG L.L.C.
Executed: 2015-08-26
Assignee
CALLAHAN CELLULAR L.L.C.
2711 CENTERVILLE RD, SUITE 400, WILMINGTON, DELAWARE, 19808
Covered Properties
(53)
Flash Memory Protection Attribute Status Bits Held in a Flash Memory Array
Patent:
5,930,826 →
Application:
08/833,599 →
Memory Device with on-Chip Manufacturing and Memory Cell Defect Detection Capability
Patent:
5,748,545 →
Application:
08/834,775 →
Node-Precise Voltage Regulation for a Mos Memory System
Patent:
5,835,420 →
Application:
08/884,251 →
Low Voltage, Low Current Hot-Hole Injection Erase and Hot-Electron Programmable Flash Memory with Enhanced Endurance
Patent:
5,953,255 →
Application:
08/998,418 →
Node-Precise Voltage Regulation for a Mos Memory System
Patent:
6,009,022 →
Application:
09/189,109 →
Reversed Split-Gate Cell Array
Patent:
6,031,765 →
Application:
09/298,032 →
Reversed Split-Gate Cell Array
Patent:
6,181,607 →
Application:
09/351,740 →
Novel Erase Condition for Flash Memory
Patent:
6,134,150 →
Application:
09/360,315 →
Bias Conditions for Repair, Program and Erase Operations of Non-Volatile Memory
Patent:
6,160,737 →
Application:
09/369,761 →
Novel Approach to Provide High External Voltage for Flash Memory Erase
Patent:
6,166,961 →
Application:
09/377,545 →
Breakdown-Free High Voltage Input Circuitry`
Patent:
6,262,622 →
Application:
09/479,649 →
Array Architecture And Process Flow Of Nonvolatile Memory Devices For Mass Storage Applications
Patent:
6,258,668 →
Application:
09/487,501 →
Stacked Gate Flash Memory Cell with Reduced Disturb Conditions
Patent:
6,660,585 →
Application:
09/531,787 →
Multiple level flash memory
Patent:
6,275,417 →
Application:
09/680,651 →
Novel approach to provide high external voltage for flash memory erase
Patent:
6,240,027 →
Application:
09/693,503 →
A Non-Volatile Semiconductor Memory Having Split-Gate Memory Cells Mirrored in a Virtual Ground Configuration
Patent:
6,717,846 →
Application:
09/696,085 →
Novel 3-Step Write Operation Nonvolatile Semiconductor One-Transistor, nor-Type Flash Eeprom Memory Cell
Patent:
6,556,481 →
Application:
09/852,247 →
Three Step Write Process Used for a Nonvolatile nor Type Eeprom Memory
Patent:
6,498,752 →
Application:
09/940,159 →
Novel Set of Three Level Concurrent Word Line Bias Conditions for a nor Type Flash Memory Array
Patent:
6,620,682 →
Application:
09/978,230 →
Two Transistor Flash Memory Cell for Use in Eeprom Arrays with a Programmable Logic Device
Patent:
6,757,196 →
Application:
10/016,898 →
Novel Method to Turn a Flash Memory into a Versatile, Low-Cost Multiple Time Programmable Eprom
Patent:
6,563,742 →
Application:
10/090,356 →
Novel Circuit Design for Accepting Multiple Input Voltages for Flash Eeprom Memory Operations
Patent:
6,574,152 →
Application:
10/104,736 →
Novel Flash Memory Array Structure Suitable for Multiple Simultaneous Operations
Patent:
6,584,034 →
Application:
10/131,271 →
Novel Eeprom Cell Structure and Array Architecture
Patent:
6,906,376 →
Application:
10/170,492 →
Novel Flash Memory Array for Multiple Simultaneous Operations
Patent:
6,628,563 →
Application:
10/191,228 →
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Patent:
6,862,223 →
Application:
10/223,208 →
Novel Parallel Channel Programming Scheme for Mlc Flash Memory
Patent:
6,714,457 →
Application:
10/233,642 →
Combination Nonvolatile Memory Using Unified Technology with Byte, Page and Block Write and Simultaneous Read and Write Operations
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Novel Highly-Integrated Flash Memory and Mask Rom Array Architecture
Novel Flash Memory Array Structure Suitable for Multiple Simultaneous Operations
Novel Flash Memory Array Structure Suitable for Multiple Simultaneous Operations
Novel Set of Three Level Concurrent Word Line Bias Conditions for a nor Type Flash Memory Array
Novel Set of Three Level Concurrent Word Line Bias Conditions for a nor Type Flash Memory Array
Array Architecture and Process Flow of Nonvolatile Memory Devices for Mass Storage Applications
Combination Nonvolatile Memory Using Unified Technology with Byte, Page and Block Write and Simultaneous Read and Write Operations
Combination Nonvolatile Memory Using Unified Technology with Byte, Page and Block Write and Simultaneous Read and Write Operations
Novel Combination Nonvolatile Integrated Memory System Using a Universal Technology Most Suitable for High-Density, High-Flexibility and High-Security Sim-Card, Smart-Card and E-Passport Applications
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Unified Non-Volatile Memory Device and Method for Integrating nor and Nand-Type Flash Memory and Eeprom Device on a Single Substrate
Novel Combo Memory Design and Technology for Multiple-Function Java Card, Sim-Card, Bio-Passport and Bio-Id Card Applications
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Nonvolatile Memory with a Unified Cell Structure
Combination Nonvolatile Memory Using Unified Technology with Byte, Page and Block Write and Simultaneous Read and Write Operations
Combination Nonvolatile Memory Using Unified Technology with Byte, Page and Block Write and Simultaneous Read and Write Operations
Nonvolatile Memory with a Unified Cell Structure
Nonvolatile Memory with a Unified Cell Structure
Related Assignments
(6)
Other recorded transfers of the patents in this record — the chain of ownership.
Nunc Pro Tunc Assignment
Dec 14, 2018
From: CALLAHAN CELLULAR L.L.C.
To: INTELLECTUAL VENTURES ASSETS 92 LLC
Reel/Frame 047780/0840 →
Assignment of Assignor's Interest
Jan 17, 2019
From: INTELLECTUAL VENTURES ASSETS 92 LLC
To: INNOMEMORY LLC
Reel/Frame 048050/0237 →
Assignment of Assignor's Interest
Jan 4, 2020
From: INTELLECTUAL VENTURES ASSETS 158 LLC
To: HANGER SOLUTIONS, LLC
Reel/Frame 051486/0425 →
Assignment of Assignor's Interest
Jan 28, 2020
From: CALLAHAN CELLULAR L.L.C.
To: INTELLECTUAL VENTURES ASSETS 158 LLC
Reel/Frame 051727/0155 →
Assignment of Assignor's Interest
Feb 17, 2021
From: INTELLECTUAL VENTURES ASSETS 152 LLC
To: DIGITAL CACHE, LLC
Reel/Frame 055280/0887 →
Assignment of Assignor's Interest
May 14, 2021
From: HANGER SOLUTIONS, LLC
To: FOOTHILLS IP LLC
Reel/Frame 056246/0533 →