EEPROM cell structure and array architecture
View Patent ↗An EEPROM cell device on a substrate is achieved. The device comprises, first, a selection transistor having gate, drain, source, and channel. The drain is defined as a cell bit line. An isolation transistor has gate, drain, source, and channel. The source is defined as a cell source line. Finally, a floating gate transistor has control gate, floating gate, drain, source, and channel. The drains and sources of each transistor comprise a diffusion layer in the substrate. The channels of each transistor comprise the substrate. The floating gate transistor drain is coupled to the selection transistor source. The floating gate transistor source is coupled to the isolation transistor drain. The device is programmed and erased by charge tunneling between the floating gate and the floating gate transistor channel. The device may further comprise an isolation well underlying the diffusion layer. A two transistor EEPROM cell is disclosed. Several array architectures using the EEPROM cell are disclosed.
1. An EEPROM cell device on a substrate, said device comprising:
a selection transistor having gate, drain, source, and channel, wherein said drain is defined as a cell bit line;
an isolation transistor having gate, drain, source, and channel, wherein said source is defined as a cell source line; and
a floating gate transistor having control gate, floating gate, drain, source, and channel, wherein said drains and sources of each said transistor comprise a diffusion layer in said substrate, wherein said channels of each said transistor comprise said substrate, wherein said floating gate transistor drain is coupled to said selection transistor source, wherein said floating gate transistor source is coupled to said isolation transistor drain, wherein said device is programmed and erased by charge tunneling between said floating gate and said floating gate transistor channel, and wherein the having a floating gate dielectric thickness between the entirety of said floating gate transistor floating gate and channel wherein said floating gate dielectric thickness is less than the gate dielectric thicknesses between said selection transistor gate and channel and between said isolation transistor gate and channel.
2. An EEPROM cell device on a substrate, said device comprising:
a selection transistor having gate, drain, source, and channel, wherein said drain is defined as a cell bit line;
an isolation transistor having gate, drain, source, and channel, wherein said source is defined as a cell source line; and
a floating gate transistor having control gate, floating gate, drain, source, and channel, wherein said drains and sources of each said transistor comprise a diffusion layer in said substrate, wherein said channels of each said transistor comprise said substrate, wherein said floating gate transistor drain is coupled to said selection transistor source, wherein
isolation transistor drain, wherein said device is programmed and erased by charge tunneling between said floating gate and said floating gate transistor channel, wherein said diffusion layer comprises a p-type doping and said substrate comprises an n-type doping and having a floating gate dielectric thickness between the entirety of said floating gate transistor floating gate and channel wherein said floating gate dielectric thickness is less than the gate dielectric thicknesses between said selection transistor gate and channel and between said isolation transistor gate and channel.