Patent Assignment
Reel/Frame 022562/0920
Assignment of Assignor's Interest
Recorded: 2009-04-21
Received: 2009-04-21
Pages: 33
Assignor
APLUS FLASH TECHNOLOGY, INC.
Executed: 2009-02-24
Assignee
ABEDNEJA ASSETS AG L.L.C.
160 GREENTREE DRIVE, SUITE 101, DOVER, DE, 19904, UNITED STATES
Covered Properties
(60)
Nonvolatile Memory with a Unified Cell Structure
Application:
12/001,647 →
Combination Nonvolatile Memory Using Unified Technology with Byte, Page and Block Write and Simultaneous Read and Write Operations
Application:
11/633,334 →
Combination Nonvolatile Memory Using Unified Technology with Byte, Page and Block Write and Simultaneous Read and Write Operations
Application:
11/633,326 →
Nonvolatile Memory with a Unified Cell Structure
Application:
11/483,241 →
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Application:
11/442,379 →
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Application:
11/391,507 →
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Application:
11/391,662 →
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Application:
11/391,170 →
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Application:
11/376,076 →
Novel Combo Memory Design and Technology for Multiple-Function Java Card, Sim-Card, Bio-Passport and Bio-Id Card Applications
Application:
11/305,700 →
Novel EEPROM cell structure and array architecture
Application:
11/091,098 →
Novel Nvram Memory Cell Architecture That Integrates Conventional Sram and Flash Cells
Application:
11/056,901 →
Unified Non-Volatile Memory Device and Method for Integrating nor and Nand-Type Flash Memory and Eeprom Device on a Single Substrate
Application:
11/040,862 →
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Application:
11/036,835 →
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Application:
11/036,945 →
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Application:
11/036,961 →
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Application:
11/036,868 →
Novel combo memory design and technology for multiple-function Javar card, SIM-card, bio-passport and bio-ID card applications
Application:
60/640,080 →
Novel Combination Nonvolatile Integrated Memory System Using a Universal Technology Most Suitable for High-Density, High-Flexibility and High-Security Sim-Card, Smart-Card and E-Passport Applications
Application:
11/025,822 →
Combination Nonvolatile Memory Using Unified Technology with Byte, Page and Block Write and Simultaneous Read and Write Operations
Application:
11/011,306 →
Combination Nonvolatile Memory Using Unified Technology with Byte, Page and Block Write and Simultaneous Read and Write Operations
Application:
11/011,304 →
Unified NVM process flow to integrate 1-transistor NOR-type flash, 1-transistor NAND-type flash and 3-transistor EEPROM onto one monolithic memory.
Application:
60/633,276 →
Noval combo nonvolatile integrated memory system using a universal technology most suitable for high-density, high-flexbility and high-security sim-card, smart-card and e-passport applications
Application:
60/631,197 →
Novel NVRAM memory cell architecture that integrates conventional SRAM and flash cells
Application:
60/591,901 →
A Non-Volatile Semiconductor Memory Having Split-Gate Memory Cells Mirrored in a Virtual Ground Configuration
Application:
10/790,579 →
Array Architecture and Process Flow of Nonvolatile Memory Devices for Mass Storage Applications
Application:
10/790,578 →
Novel Set of Three Level Concurrent Word Line Bias Conditions for a nor Type Flash Memory Array
Application:
10/627,183 →
Novel Set of Three Level Concurrent Word Line Bias Conditions for a nor Type Flash Memory Array
Application:
10/627,834 →
Stacked gate flash memory cell with reduced disturb conditions
Application:
10/616,751 →
Novel Flash Memory Array Structure Suitable for Multiple Simultaneous Operations
Application:
10/423,558 →
Novel Flash Memory Array Structure Suitable for Multiple Simultaneous Operations
Application:
10/423,559 →
Novel Highly-Integrated Flash Memory and Mask Rom Array Architecture
Application:
10/364,033 →
Novel Highly-Integrated Flash Memory and Mask Rom Array Architecture
Application:
10/353,584 →
Combination Nonvolatile Memory Using Unified Technology with Byte, Page and Block Write and Simultaneous Read and Write Operations
Application:
10/351,179 →
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Application:
10/351,180 →
Novel monolithic, combo nonvolatile memory allowing simultaneous read and write operations, and byte, page and block write at any random location with no disturb using a unified cell structure and technology with a new scheme of decoder and layout
Application:
60/429,261 →
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Application:
60/426,614 →
Novel Parallel Channel Programming Scheme for Mlc Flash Memory
Application:
10/233,642 →
Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout
Application:
10/223,208 →
Novel Flash Memory Array for Multiple Simultaneous Operations
Application:
10/191,228 →
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder
Application:
60/394,202 →
Novel Eeprom Cell Structure and Array Architecture
Application:
10/170,492 →
Novel Flash Memory Array Structure Suitable for Multiple Simultaneous Operations
Application:
10/131,271 →
Novel Circuit Design for Accepting Multiple Input Voltages for Flash Eeprom Memory Operations
Application:
10/104,736 →
Novel Method to Turn a Flash Memory into a Versatile, Low-Cost Multiple Time Programmable Eprom
Application:
10/090,356 →
Novel highly-integrated flash memory and mask ROM array architecture
Application:
60/359,696 →
Bit-By-Bit Vt-Correction Operation for Nonvolatile Semiconductor One-Transistor Cell, nor-Type Flash Eeprom
Application:
10/076,826 →
Two Transistor Flash Memory Cell for Use in Eeprom Arrays with a Programmable Logic Device
Application:
10/016,898 →
Novel Set of Three Level Concurrent Word Line Bias Conditions for a nor Type Flash Memory Array
Application:
09/978,230 →
Novel parallel-channel-programming scheme for MLC flash
Application:
60/323,245 →
Three Step Write Process Used for a Nonvolatile nor Type Eeprom Memory
Application:
09/940,159 →
Novel flash memory array for multiple simultaneous operations
Application:
60/303,869 →
Novel 3-Step Write Operation Nonvolatile Semiconductor One-Transistor, nor-Type Flash Eeprom Memory Cell
Application:
09/852,247 →
Novel flash memory array structure suitable for multiple simultaneous operations
Application:
60/285,750 →
Novel input circuit design that can accept more than 3 input voltages for different operations of EEPROM flash EEPROM memory
Application:
60/280,342 →
Highly-scalable, two-transistor flash EEPROM cells, cell arrays and preferred opration schemers for in-system programmable logic device with simplified on-chip state machine
Application:
60/277,852 →
Bit-by-bit Vt correction operation for nonvolatile semiconductor one-transistor-cell, NOR-type flash EEPROM
Application:
60/273,585 →
Novel method to turn a flash memory into a versatile, low-cost MTP EPROM
Application:
60/273,002 →
Novel set of 3-level concurrent wordline bias conditions for nonvolatile semiconductor one-transistor-cell, NOR-type flash EEPROM memory array
Application:
60/271,644 →
Novel 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash eeprom memory array
Application:
60/270,422 →