Stacked semiconductor device
View Patent ↗As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.
1. A stacked semiconductor device, comprising:
core chips,
an interface chip,
an interposer, and
a defective contact recovery means which has an auxiliary recovery signal path for signal paths,
wherein the signal paths are formed by through electrodes extending through the core chips and contact portions between the through electrodes of the core chips.
2. The stacked semiconductor device according to claim 1 , wherein:
the defective contact recovery means comprises a parallel arrangement system in which the auxiliary recovery signal path is provided for one line of the signal paths.
3. The stacked semiconductor device according to claim 2 , wherein:
the parallel arrangement system is applied to a signal inputted from an exterior of the stacked semiconductor device.
4. The stacked semiconductor device according to claim 2 , wherein:
the parallel arrangement system is applied to a signal transmitted as serial data between an external terminal and the interface chip.
5. The stacked semiconductor device according to claim 1 , wherein: the defective contact recovery means comprises a defective contact recovery circuit system in which the auxiliary recovery signal path is provided for n lines (n: an integer larger than 0) of the signal paths, and
the signal paths are switched by a defective contact recovery circuit.
6. The stacked semiconductor device according to claim 5 , wherein:
the defective contact recovery circuit is mounted on the core chips.
7. The stacked semiconductor device according to claim 6 , wherein:
the defective contact recovery circuit includes a latch circuit for memorizing a defective contact portion, a change-over switch, and a control circuit.
8. The stacked semiconductor device according to claim 7 , wherein:
the defective contact recovery circuit system is applied to a signal having a large number of lines between the interface chip and the core chips.
9. The stacked semiconductor device according to claim 7 , wherein:
the defective contact recovery circuit system is applied to a signal which is subjected to a parallel conversion between the interface chip and the core chips and is to be transmitted to an exterior of the stacked semiconductor device.
10. The stacked semiconductor device according to claim 1 , wherein:
different defective contact recovery means are used for the signal paths in the stacked semiconductor device.
11. The stacked semiconductor device according to claim 10 , wherein:
a parallel arrangement system is used as the defective contact recovery means for a signal path to an input/output circuit connected to an external terminal, and
a defective contact recovery circuit is used as the defective contact recovery means for a signal path to an input/output circuit connected to the core chips.
12. The stacked semiconductor device according to claim 10 , wherein:
the core chips have a memory cell of a DRAM and a peripheral circuit of the memory cell,
the interface chip has an external input/output circuit connected to an external terminal and an internal signal input/output circuit connected to the core chips,
a parallel arrangement system is used as the defective contact recovery means for a signal path to the external input/output circuit, and
a defective contact recovery circuit is used as the defective contact recovery means for a signal path to the internal signal input/output circuit.
13. The stacked semiconductor device according to claim 12 , wherein:
the stacked semiconductor device comprises a DDR type DRAM operable to input and output a data signal having a burst length of at least 2.