Systems and methods for managing power

1. A system for managing power of a memory array, the system comprising:

a comparator configured to compare a first voltage with a reference voltage, the first voltage corresponding to an operating voltage of at least one of a peripheral circuit associated with the memory away and a logic circuit configured to communicate with the peripheral circuit, the reference voltage corresponding to a minimum threshold voltage for read/write operations of the memory array;

selection circuitry configured to provide a selected signal based on the output of the comparator, the selected signal being the greater of the first voltage and the reference voltage; and

an output circuit configured to provide an output voltage to the memory array in response to the selected signal, the output voltage being the greater of the operating voltage of the at least one of the peripheral circuit and the logic circuit and the minimum threshold voltage.

2. The system of claim 1 , wherein the output circuit comprises a field effect transistor (FET) interconnected between a positive supply voltage and the memory array.

3. The system of claim 2 , wherein the positive supply voltage is an input/output supply voltage of an integrated circuit that comprises the memory array.

4. The system of claim 1 , wherein the memory array is one of a plurality of memory arrays, and wherein a switch provides the output voltage to the plurality of memory arrays.

5. A mobile communication device comprising the system of claim 1 .

6. A system for managing power of a memory array, the system comprising:

a comparator configured to compare a first voltage with a reference voltage, the first voltage corresponding to an operating voltage of at least one of a peripheral circuit associated with the memory away and a logic circuit configured to communicate with the peripheral circuit, the reference voltage corresponding to a minimum threshold voltage for read/write operations of the memory array; and

an output circuit configured to provide an output voltage to the memory array in response to an output of the comparator:

wherein the output circuit is configured to output the greater of the first voltage and the reference voltage to the memory away in an active mode of operation associated with the memory array, and is further configured to output a predetermined voltage in a retention mode of operation associated with the memory array.

7. A system for managing power of a memory array, the system comprising:

a comparator configured to compare a first voltage with a reference voltage, the first voltage corresponding to an operating voltage of at least one of a peripheral circuit associated with the memory away and a logic circuit configured to communicate with the peripheral circuit, the reference voltage corresponding to a minimum threshold voltage for read/write operations of the memory array; and

an output circuit configured to provide an output voltage to the memory array in response to an output of the comparator, the output voltage being the greater of the operating voltage of the at least one of the peripheral circuit and the logic circuit and the minimum threshold voltage, wherein the output circuit comprises:

a field effect transistor (FET) interconnected between a positive supply voltage and the memory array, the positive supply voltage is an input/output supply voltage of an integrated circuit that comprises the memory array; and

an operational amplifier having a variable output coupled to a gate terminal of the FET, the operational amplifier being configured to control the FET in a substantially linear mode, such that the FET provides the output voltage based on scaling-down the positive supply voltage.

8. The system of claim 7 , wherein the operational amplifier provides the variable output based on a first input that is a fractionally scaled version of the greater of the first voltage and the reference voltage and a second input that is a fractionally scaled version of the output voltage.

9. The system of claim 8 , wherein the comparator is disabled in response to a retention mode activation signal.

10. A method for managing power of a memory array, the method comprising:

comparing a first voltage with a reference voltage, the first voltage corresponding to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit, the reference voltage corresponding to a minimum threshold voltage for read/write operations of the memory array;

selecting the greater of the first voltage and the reference voltage in response to the comparison of the first voltage and the reference voltage; and

providing a memory supply voltage to the memory array in response to the the selecting of the greater of the first voltage and the reference voltage, the memory supply voltage being the greater of the minimum threshold voltage and the operating voltage of the at least one of the peripheral circuit and the logic circuit.

11. The method of claim 10 , further comprising selecting between an active mode of the memory array and a retention mode of the memory array.

12. The method of claim 10 , wherein the memory array is one of a plurality of memory arrays, and wherein the providing the memory supply voltage comprises providing the memory supply voltage to the plurality of memory arrays.

13. A mobile communication device configured to implement the method of claim 10 .

14. A method for managing power of a memory array, the method comprising:

comparing a first voltage with a reference voltage, the first voltage corresponding to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit, the reference voltage corresponding to a minimum threshold voltage for read/write operations of the memory array; and

providing a memory supply voltage to the memory array in response to the comparison of the first voltage and the reference voltage, the memory supply voltage being the greater of the minimum threshold voltage and the operating voltage of the at least one of the peripheral circuit and the logic circuit;

wherein the providing the memory supply voltage comprises scaling-down a positive supply voltage to a magnitude that is approximately equal to the greater of the minimum threshold voltage and the operating voltage of the at least one of the peripheral circuit and the logic circuit.

15. The method of claim 14 , further comprising providing the positive supply voltage from an input/output supply voltage on an integrated circuit that comprises the memory array.

16. The method of claim 14 , wherein the scaling-down comprises operating a field effect transistor (FET) in a linear mode based on a variable output of an operational amplifier.

17. The method of claim 16 , further comprising providing a first input to the operational amplifier, the first input being a scaled version of the memory supply voltage, and providing a second input to the operational amplifier, the second input being a scaled version of the greater of the first voltage and the reference voltage, the operational amplifier providing a gate voltage to the FET based on the first input and the second input.

18. A method for managing power of a memory array, the method comprising:

comparing a first voltage with a reference voltage, the first voltage corresponding to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit, the reference voltage corresponding to a minimum threshold voltage for read/write operations of the memory array;

providing a memory supply voltage to the memory array in response to the comparison of the first voltage and the reference voltage, the memory supply voltage being the greater of the minimum threshold voltage and the operating voltage of the at least one of the peripheral circuit and the logic circuit; and

selecting between an active mode of the memory array and a retention mode of the memory array;

wherein the providing the memory supply voltage comprises providing the greater of the first voltage and the reference voltage as the memory supply voltage if the active mode is selected, and providing a predetermined voltage as the memory supply voltage if the retention mode is selected.

19. A system for managing power of a memory array, the system comprising:

means for comparing a first voltage with a reference voltage, the first voltage corresponding to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit, the reference voltage corresponding to a minimum threshold voltage for read/write operations of the memory array;

means for selecting the greater of the first voltage and the reference voltage in response to the means for comparing; and

means for providing a memory supply voltage to the memory array in response to the means for selecting, the memory supply voltage being the greater of the minimum threshold voltage and the operating voltage of the at least one of the peripheral circuit and the logic circuit.

20. A system for managing power of a memory array, the system comprising:

means for comparing a first voltage with a reference voltage, the first voltage corresponding to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit, the reference voltage corresponding to a minimum threshold voltage for read/write operations of the memory array; and

means for providing a memory supply voltage to the memory array in response to the means for comparing, the memory supply voltage being the greater of the minimum threshold voltage and the operating voltage of the at least one of the peripheral circuit and the logic circuit;

wherein the positive supply voltage is an input/output supply voltage of an integrated circuit that comprises the memory array, wherein the means for providing the memory supply voltage further comprises means for scaling-down the positive supply voltage to provide the memory supply voltage.

21. A system for managing power of a memory array, the system comprising:

means for comparing a first voltage with a reference voltage, the first voltage corresponding to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit, the reference voltage corresponding to a minimum threshold voltage for read/write operations of the memory array;

means for providing a memory supply voltage to the memory array in response to the means for comparing, the memory supply voltage being the greater of the minimum threshold voltage and the operating voltage of the at least one of the peripheral circuit and the logic circuit; and

means for switching the output voltage to a predetermined voltage in a retention mode, such that the means for providing the output voltage provides the greater of the minimum threshold voltage and the operating voltage of the at least one of the peripheral circuit and the logic circuit in an active mode and provides the predetermined voltage in the retention mode.