Method of forming compressive channel layer of PMOS device using gate spacer and PMOS device having a compressed channel layer
View Patent ↗A method of forming a compressive channel layer in a PMOS device and a PMOS device having a compressive channel layer are provided. The method includes (a) forming a buffer oxide layer on a silicon semiconductor substrate having a gate oxide layer and a gate electrode thereon, (b) forming a silicon nitride layer on the buffer oxide layer, (c) implanting impurities into the silicon nitride layer, and (d) etching or patterning the silicon nitride layer and the buffer oxide layer into which impurities are implanted to form gate spacers on sidewalls of the gate electrode.
1. A method of forming a PMOS device, the method comprising the steps of:
forming a buffer oxide layer on a silicon semiconductor substrate having a gate oxide layer and a gate electrode thereon;
forming a silicon nitride layer on the buffer oxide layer;
implanting germanium (Ge) into the silicon nitride layer at an ion implantation energy of 30-50 KeV and at a dose of 10 12 -10 13 cm −2 , thereby compressing a channel region of the substrate below the gate electrode; and
patterning the silicon nitride layer and the buffer oxide layer into which germanium is implanted, thereby forming gate spacers on sidewalls of the gate electrode.
2. The method of claim 1 , wherein implanting the impurities compresses the silicon nitride layer.
3. A method of forming a PMOS device, the method comprising the steps of:
forming a buffer oxide layer on a silicon semiconductor substrate having a gate oxide layer and a gate electrode thereon;
forming a silicon nitride layer on the buffer oxide layer;
implanting germanium (Ge) into the silicon nitride layer at an ion implantation energy of 30-50 KeV and at a dose of 10 12 -10 13 cm −2 to compress the silicon nitride layer and a channel region of the substrate below the gate electrode; and
etching the silicon nitride layer containing implanted germanium and the buffer oxide layer to form gate spacers on sidewalls of the gate electrode.
4. The method of claim 1 , further comprising forming a silicon oxide layer on the silicon nitride layer.
5. The method of claim 4 , wherein patterning the silicon nitride layer and the buffer oxide layer further comprises patterning the silicon oxide layer.
6. The method of claim 3 , further comprising forming a silicon oxide layer on the silicon nitride layer.
7. The method of claim 6 , wherein etching the silicon nitride layer and the buffer oxide layer further comprises etching the silicon oxide layer.
8. The method of claim 1 , wherein forming the buffer oxide layer comprises forming the buffer oxide layer to a thickness of about 200 Å, and forming the silicon nitride layer comprises forming the silicon nitride layer to a thickness of about 200 Å.
9. The method of claim 3 , wherein forming the buffer oxide layer comprises forming the buffer oxide layer to a thickness of about 200 Å, and forming the silicon nitride layer comprises forming the silicon nitride layer to a thickness of about 200 Å.
10. The method of claim 1 , wherein implanting impurities into the silicon nitride layer increases a carrier mobility in the channel region.
11. The method of claim 3 , wherein implanting impurities into the silicon nitride layer increases a carrier mobility in the channel region.