JPEG image processing circuit
A JPEG image processing circuit, capable of performing a JPEG process at high speed, and with low power consumption, and of automatically recovering from a slight trouble, has been disclosed. In the JPEG processing circuit, a JPEG processing section is configured so as to comprise a plurality of JPEG processing cores and a plurality of data storage regions provided in correspondence with the plurality of JPEG processing cores, and when each of the JPEG processing cores performs the process in parallel, the unprocessed data required for the process of each of the JPEG processing cores is stored in each of the data storage regions, corresponding to each of the JPEG processing cores, via a common bus connected to an image memory.
1. A JPEG image processing circuit comprising:
a common bus connected to an image memory; and
a JPEG processing section that is connected to the common bus, processes unprocessed data obtained from the image memory via the common bus in the JPEG format, and outputs processed data to the image memory via the common bus, wherein:
the JPEG processing section comprises a plurality of JPEG processing cores and a plurality of data storage regions provided in correspondence with the plurality of the JPEG processing cores; and
when each of the JPEG processing cores performs the process, the part of the unprocessed data required for the process of each of the JPEG processing cores is stored in each of the data storage regions corresponding to each of the JPEG processing cores.
2. The JPEG image processing circuit as set forth in claim 1 , wherein the processed data in each of the JPEG processing cores is output to the image memory via the common bus after being stored in the corresponding data storage region.
3. The JPEG image processing circuit as set forth in claim 1 , wherein the amount of unprocessed data to be stored in each of the data storage regions can be set arbitrarily.
4. The JPEG image processing circuit as set forth in claim 1 , wherein the amount of unprocessed data to be stored in each of the data storage regions can be varied dynamically.
5. The JPEG image processing circuit as set forth in claim 1 , wherein the amount of unprocessed data to be stored in each of the data storage regions is the minimum encoding unit (MCU) of the JPEG process.
6. The JPEG image processing circuit as set forth in claim 1 , wherein:
the JPEG processing section comprises a control section; and
the control section changes the use method of the plurality of JPEG processing cores in accordance with the operation mode.
7. The JPEG image processing circuit as set forth in claim 1 , wherein:
the JPEG processing section comprises a control section; and
the control section dynamically changes the number of JPEG processing cores in operation from among the plurality of JPEG processing cores.
8. The JPEG image processing circuit as set forth in claim 1 , wherein the JPEG processing section comprises an operation clock control section that sets the operation clock frequency of each of the JPEG processing cores in accordance with the operation.
9. The JPEG image processing circuit as set forth in claim 8 , wherein the operation clock control section dynamically varies the operation clock frequency of each of the JPEG processing cores.
10. The JPEG image processing circuit as set forth in claim 1 , wherein:
the JPEG processing section comprises a control section; and
the control section automatically detects the occurrence of trouble in the plurality of the JPEG processing cores and indicates the trouble that has occurred.
11. The JPEG image processing circuit as set forth in claim 10 , wherein the control section assigns the process of the JPEG processing core in which the trouble has occurred to another JPEG processing core to continue the process based on the trouble indication.
12. The JPEG image processing circuit as set forth in claim 11 , wherein:
the control section monitors the processing time in each of the JPEG processing cores and detects the occurrence of trouble by judging that a time-out of the processing time has exceeded a reference time; and
the time-out judgment is performed by detecting the elapsed time after the process starts by the absolute time timer of the JPEG processing core and comparing the elapsed time with the reference time.
13. The JPEG image processing circuit as set forth in claim 12 , wherein the control section changes the reference time when the process is started again after the time-out has occurred.