Voltage level shifter with single well voltage
This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.
1. A voltage level shifter with reduced layout area, comprising:
an inverter including a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate coupled to an input terminal, a source coupled to a first positive voltage (VDDL) and a first bulk formed within a Nwell coupled to a second positive voltage (VDD) which is higher than VDDL;
a second PMOS transistor with its gate coupled to the inverter via an NMOS transistor, the second PMOS transistor has a source and a second bulk formed within said Nwell coupled to the VDD, and a drain coupled to an output node; and
a third PMOS transistor having a gate coupled to the output node, a source and a third bulk formed within said Nwell coupled to the VDD, and a drain coupled to the gate of the second PMOS transistor, respectively, such that the VDDL voltage level at the input terminal is shifted to the VDD voltage level at the output node.
2. The voltage level shifter of claim 1 further comprising:
a first N-type metal-oxide-semiconductor (NMOS) transistor having a gate, a drain and a source coupled to the input terminal, a drain of the first PMOS transistor and a complementary low voltage power supply (GND), respectively;
a second NMOS transistor having a gate, a drain and a source coupled to the drain of the first NMOS transistor, a gate of the second PMOS transistor and the GND, respectively; and
a third NMOS transistor having a gate, a drain and a source coupled to the input terminal, the output node and the GND, respectively.
3. The voltage level shifter of claim 2 further comprising an inverter having an input and an output coupled to the output node and an output terminal, respectively.
4. The voltage level shifter of claim 2 , wherein the third PMOS transistor is serially connected to the second NMOS transistor.
5. A voltage level shifter with reduced layout area, comprising:
a first inverter including a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate coupled to an input terminal, a source coupled to a first positive voltage (VDDL) and a first bulk formed within a Nwell coupled to a second positive voltage (VDD) which is higher than the VDDL;
a second PMOS transistor with its gate coupled to the inverter via an NMOS transistor, the second PMOS transistor has a drain coupled to an output node, and both a source and a second bulk formed within said Nwell coupled to the VDD;
a third PMOS transistor having a gate coupled to the output node, a source and a third bulk formed within said Nwell coupled to the VDD, and a drain coupled to the gate of the second PMOS transistor, respectively; and
a second inverter coupled between the drain of the second PMOS transistor and an output terminal (OUT), such that the VDDL voltage level at the input terminal is shifted to the VDD voltage level at the output node.
6. The voltage level shifter of claim 5 further comprising:
a first N-type metal-oxide-semiconductor (NMOS) transistor having a gate, a drain and a source coupled to the input terminal, a drain of the first PMOS transistor and a complementary low voltage power supply (GND), respectively;
a second NMOS transistor having a gate, a drain and a source coupled to the drain of the first NMOS transistor, a gate of the second PMOS transistor and the GND, respectively; and
a third NMOS transistor having a gate, a drain and a source coupled to the input terminal, the output node and the GND, respectively.
7. The voltage level shifter of claim 6 , wherein the inverter is coupled to the VDD and GND, respectively.
8. The voltage level shifter of claim 6 , wherein the third PMOS transistor is serially connected to the second NMOS transistor.