Address mark detection with error threshold that varies with timing jitter

1. An apparatus, comprising:

an address mark detector having an address mark output, the address mark output being indicated as erroneous when errors in a detected address mark exceed an error threshold function, the error threshold function having a variation as a function of a difference between a detected address mark time and a reference address mark time.

2. The apparatus of claim 1 wherein the error threshold function permits a larger number of errors closer to the reference address mark time, and permits a decreasing number of errors farther from the reference address mark time.

3. The apparatus of claim 1 wherein the address mark detector comprises an address mark time output , and the apparatus comprises a function generator that comprises:

a reference circuit providing the reference address mark time;

a timing error comparator that receives the reference address mark time and the address mark time output, and that generates a comparator output; and

a threshold selector that receives the comparator output and that generates the error threshold function.

4. The apparatus of claim 1 wherein the indicating of the address mark as erroneous comprises suppressing the address mark output.

5. The apparatus of claim 4 wherein the suppressing of the address mark output comprises repeating a preceding unsuppressed address mark that is adjusted for head travel.

6. The apparatus of claim 1 wherein the detected address mark has timing that is controlled by a disc locked clock.

7. A method, comprising:

detecting a number of bit errors and a time position of a detected address mark;

calculating an error threshold function as a function of a difference between the time position of the address mark and a reference address mark time; and

providing an address mark output that is indicated as erroneous if the number of bit errors exceed the error threshold function.

8. The method of claim 7 , comprising:

shaping the error threshold function to permit a larger number of bit errors closer to the nominal time, and to permit a decreasing number of errors farther from the nominal time.

9. The method of claim 7 , comprising:

providing an address mark time output;

providing a reference time output; and

generating a comparison of the address mark time output and the reference time output.

10. The method of claim 7 , comprising:

controlling timing of the address mark detector with a disc locked clock.

11. The method of claim 7 , comprising:

generating an address mark time output;

providing a reference time output;

generating a comparator output that represents timing error of the address mark time output with respect to the reference time output; and

generating the error threshold function as a function of the comparator output.

12. The method of claim 7 wherein multiple error threshold functions are generated, and one of the multiple error threshold functions is selectable for use.

13. The method of claim 7 wherein the indicating as erroneous comprises suppressing the address mark output.

14. The method of claim 7 wherein the indicating as erroneous comprises repeating a preceding non-erroneous address mark that is adjusted for head travel.